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d a t a sh eet preliminary speci?cation 2003 nov 18 integrated circuits SAA7724H car radio digital signal processor
2003 nov 18 2 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H contents 1 features 2 general information 2.1 dsp radio system 2.2 SAA7724H 2.3 sample rates 3 ordering information 4 block diagram 5 pinning 6 functional description 6.1 voltage regulator 6.2 audio analog front-end 6.2.1 selector diagram 6.2.2 realization of the common mode input with ain 6.2.3 realization of the differential adiff input 6.2.4 realization of the auxiliary input with volume control 6.2.5 supplies and references 6.3 ad decimation paths (dad) 6.3.1 ldf and aux decimation path 6.3.2 adf and audio decimation path 6.4 digital audio input/output 6.4.1 general 6.4.2 external i 2 s-bus input/output ports 6.4.3 external spdif input 6.4.4 epics host i 2 s-bus port 6.5 sample rate converter 6.6 if_ad 6.6.1 if_ad single block diagram 6.6.2 if_ad detailed functional description 6.7 audio_epics specific information 6.7.1 audio_epics start-up 6.7.2 audio_epics memory overview 6.8 sdac output path 6.8.1 dac upsampling filter 6.8.2 dac noise shaper 6.8.3 dac codem scrambler 6.8.4 multi-bit sdac 6.8.5 analog summer function 6.8.6 sdac application diagram 6.9 reset block functional overview 6.9.1 asynchronous reset 6.10 clock circuit and oscillator 6.10.1 circuit description 6.10.2 external clock input mode 6.10.3 crystal oscillator supply 6.10.4 application guidelines 6.11 pll circuits 6.12 rds 6.12.1 general description 6.12.2 rds i/o modes 6.12.3 rds demodulator 6.12.4 rds bit buffer 6.12.5 rds/rbds decoder 7 limiting values 8 thermal resistance 9 dc characteristics 10 ac characteristics 10.1 timing diagrams 11 i 2 c-bus control 11.1 i 2 c-bus protocol 11.1.1 protocol of the i 2 c-bus commands 11.2 mpi data transfer formats 11.3 reset initialization 11.4 defined i 2 c-bus address 11.5 i 2 c-bus memory map specification 12 i 2 s-bus control 12.1 basic system requirements 12.2 serial data 12.3 word select 13 package outline 14 soldering 14.1 introduction to soldering surface mount packages 14.2 reflow soldering 14.3 wave soldering 14.4 manual soldering 14.5 suitability of surface mount ic packages for wave and reflow soldering methods 15 data sheet status 16 definitions 17 disclaimers 18 purchase of philips i 2 c components
2003 nov 18 3 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 1 features am and fm digitize at if am and fm narrow-band/if agc am and fm if filtering am and fm adjustable channel detection/variable if if filter for wx am and fm demodulation am and fm stereo decoding am and fm stereo pilot detection fm pilot notch am pilot filter fm stereo blend, high blend, high cut, soft muting and de-emphasis am stereo blend, lp filter, high cut and soft muting am and fm noise blanker am and fm gain adjust and calibration (audio) fm multipath detection fm multipath correction diversity switching radio data system (rds) and radio broadcast data system (rbds) demodulation and decoding tape head calibration, equalization, dolby b and ams (from analog tape input) cd gain adjust, calibration and compression (from analog or digital spdif/i 2 s-bus input) parametric equalization volume control bass control treble control balance/fade control dc blocking filter dual source select dual playback channel delays analog summer for four channels (through inputs mono1 and mono2) audio limiting. 1.1 sample rates the SAA7724H runs at a master clock of 43.2 mhz. audio processing runs at a sample rate of 1f s 42.1875 khz 43.2 mhz 1024 ------------------------- - ==
2003 nov 18 4 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 2 general information 2.1 dsp radio system the digital signal processing (dsp) radio system (see fig.1) consists of: analog tuner (also called rf/if) SAA7724H audio power amplifier microcontroller if co-processor audio co-processor. the microcontroller interfaces to the rf/if and SAA7724H via an i 2 c-bus. analog tape and cd inputs are input from other parts of the radio. the if co-processor and audio co-processor interfaces to the SAA7724H via an i 2 s-bus. 2.2 SAA7724H the SAA7724H digitizes up to two if signals and performs dsp to generate left front, right front, left rear, and right rear audio and rds/rbds data output. the SAA7724H also samples analog baseband tape, fm mpx, aux inputs, analog and digital cd, performs signal processing on these sampled waveforms and multiplexes the proper signal to the output. a microcontroller interface allows the SAA7724H to be controlled and monitored. the SAA7724H is composed of hardwired and programmable dsp circuitry, with programmable parameters, such as injection frequencies, filter coefficients and control parameters. some functions or groups of functions are implemented with programmable sequence processors. handbook, full pagewidth mgw194 audio co-processor if co-processor audio power amplifier analog tuner 10.7 mhz/fm 450 khz/am if SAA7724H micro- controller tape, cd analog, aux, cd digital, fm mpx i 2 s- bus i 2 c- bus i 2 s- bus fig.1 system overview.
2003 nov 18 5 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 3 ordering information type number package name description version SAA7724H qfp100 plastic quad ?at package; 100 leads (lead length 1.95 mm); body 14 20 2.8 mm sot317-3
2003 nov 18 6 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 4 block diagram handbook, full pagewidth mgw191 mpx2 flag mpx1 swb and interfaces ifp boot rom ifp i 2 s-bus src_1 extiis_1 spdif_1 ldf_1 1 16 4 comp filter aux1_sel_lev_voice lpf_1 auxad_1 if_ad and dither if_ad and dither src_2 dit1 dit2 extiis_2 spdif_2 ldf_2 16 4 comp filter aux2_sel_lev_voice lpf_2 auxad_2 selector 85 86 3 2 5 4 99 100 97 98 89 88 87 96 95 94 14 20 21 22 25 24 23 15 82 83 84 38 39 40 41 42 43 35 47 46 aad adf1_1 16 audioad_1 adf2_1 8 dc offset sat adf1_2 aad2h aad1h ifss2h ifss1h aad2l aad1l ifss2l ifss1l 16 audioad_2 adf2_2 8 dc offset sat ch1_wide_narrow ch2_wide_narrow ch2_dc_offset ch1_dc_offset 8 9 10 26 33 34 44 45 58 v ss(i/o4) v dd(reg) mono1_p mono1_n mono2_p mono2_n vdacn v dda2 vdacp spdif1 spdif2 ext_iis_ws1 ext_iis_bck1 ext_iis_io1 ext_iis_ws2 ext_iis_bck2 ext_iis_io2 v ss(i/o1) v ss(i/o2) v dd(i/o2) ifp_iis_out5 ifp_iis_in1 ifp_iis_i2o6 ifp_iis_i3o4 ifp_iis_out1 ifp_iis_out2 ifp_iis_out3 v dd(i/o3) v ss(i/o3) ifp_iis_bck ifp_iis_ws adiff_rn adiff_rp adiff_ln adiff_lp ain2_r ain2_ref ain2_l ain1_r ain1_ref ain1_l ifss2 ifss1 if_in2 if_vg if_in1 SAA7724H c b a d e f g src-epics bus swb-epics bus and flag ifp status fig.2 block diagram (continued in fig.3).
2003 nov 18 7 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H handbook, full pagewidth mgw192 reset pll1 oscillator and clock rdsdec_1 rdsdem_1 mpi rds sel_rds_clk1_davn2 sel_davn2_rds_flag 50 51 52 53 49 48 13 17 19 18 75 78 77 76 16 ifp status swb-epics bus and lflag src-epics bus epics i 2 s-bus pll2 audio_epics src_epics tcb iic_reg dio noise shaper interpolator sdac_f f r 128 sdac_r audio_epics ch.st. spdif_1 ch.st. spdif_2 lock spdif_1 lock spdif_2 rdsdec_2 rdsdem_2 28 27 29 37 12 11 6 7 36 30 31 32 54 55 56 57 59 60 61 62 63 80 vrefif 79 v ss(if) v dd(osc) osc_out osc_in v ss(osc) 71 v ssd3 70 v ddd3 69 v ssd5 68 v ssd2 67 v ddd2 66 v ssd1 65 v ddd1(mem) 64 v ssd6 dsp_io8 dsp_io7 dsp_io6 dsp_io5 dsp_io4 dsp_io3 dsp_io2 dsp_io1 dsp_io0 rds_data1_davn1 rds_clk1_davn2 rds_data2 rrv lrv rfv lfv a0 reset tscan shtcb iis_in1 iis_in2 iis_in3 iis_out1 iis_out2 iis_out3 iis_bck iis_ws scl sda rds_clk2 93 vrefad 92 vadcn 91 vadcp 90 v dda1 81 v dd(if) SAA7724H rtcb g f e d c b a voltage regulator conreg gapreg febreg 72 74 73 mpx2 mpx1 flag fig.3 block diagram (continued from fig.2)
2003 nov 18 8 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 5 pinning table 1 functional pin description symbol pin description v dd(reg) 1 supply voltage for 2.5 v regulator circuit and bias for adcs (3.3 v) mono1_p 2 differential positive analog input to aux_ad2, audioad_1 and audioad_2 mono1_n 3 differential negative analog input to aux_ad2, audioad_1 and audioad_2 mono2_p 4 differential positive analog input to aux_ad2, audioad_1 and audioad_2 mono2_n 5 differential negative analog input to aux_ad2, audioad_1 and audioad_2 rrv 6 analog audio voltage output for the right-rear speaker lrv 7 analog audio voltage output for the left-rear speaker vdacn 8 negative reference voltage for the sdac v dda2 9 analog supply voltage for the sdac (2.5 v) vdacp 10 positive reference voltage for the sdac rfv 11 analog audio voltage output for the right-front speaker lfv 12 analog audio voltage output for the left-front speaker a0 13 slave subaddress for i 2 c-bus selection spdif1 14 spdif input channel 1 from digital media source spdif2 15 spdif input channel 2 from digital media source reset 16 reset input (active low) tscan 17 scan control shtcb 18 shift clock test control block r tcb 19 asynchronous reset test control block (active low) ext_iis_ws1 20 word select input from digital media source 1 (i 2 s-bus) ext_iis_bck1 21 bit clock input from digital media source 1 (i 2 s-bus) ext_iis_io1 22 data input/output digital media source 1 (i 2 s-bus) ext_iis_ws2 23 word select input from digital media source 2 (i 2 s-bus) ext_iis_bck2 24 bit clock input from digital media source 2 (i 2 s-bus) ext_iis_io2 25 data input/output digital media source 2 (i 2 s-bus) v ss(i/o1) 26 ground supply 1 for external digital ports iis_in1 27 data channel input 1 (front channels) from external dsp ic (i 2 s-bus) iis_in2 28 data channel input 2 (rear channels) from external dsp ic (i 2 s-bus) iis_in3 29 data channel input 3 from external dsp ic (i 2 s-bus) iis_out1 30 data channel output 1 for external dsp ic activated by en_host_io (i 2 s-bus) iis_out2 31 data channel output 2 to external dsp ic activated by en_host_io (i 2 s-bus) iis_out3 32 data channel output 3 to external dsp ic activated by en_host_io (i 2 s-bus) v ss(i/o2) 33 ground supply 2 for external digital ports v dd(i/o2) 34 supply voltage 2 for external digital ports (3.3 v) ifp_iis_out5 35 ifp data channel output 5 to external dsp ic activated by ifp_iis_en; can also be used as 256 f s clock output enabled by en_256fs (i 2 s-bus) iis_bck 36 clock output for external dsp ic enabled by en_host_io (i 2 s-bus) iis_ws 37 word select output for external dsp ic enabled by en_host_io (i 2 s-bus) ifp_iis_in1 38 ifp data channel input 1 from external dsp ic (i 2 s-bus)
2003 nov 18 9 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H ifp_iis_i2o6 39 ifp data channel input 2 from external dsp ic or output data channel 6 to external dsp ic selected by ifp_iis_io_mode (i 2 s-bus) ifp_iis_i3o4 40 ifp data channel input 3 from external dsp ic or output data channel 4 to external dsp ic selected by ifp_iis_io_mode (i 2 s-bus) ifp_iis_out1 41 ifp data channel output 1 to external dsp ic activated by ifp_iis_en (i 2 s-bus) ifp_iis_out2 42 ifp data channel output 2 to external dsp ic activated by ifp_iis_en (i 2 s-bus) ifp_iis_out3 43 ifp data channel output 3 to external dsp ic activated by ifp_iis_en (i 2 s-bus) v dd(i/o3) 44 supply voltage 3 for external digital ports (3.3 v) v ss(i/o3) 45 ground supply 3 for external digital ports ifp_iis_bck 46 ifp output clock for external dsp ic enabled by ifp_iis_en (i 2 s-bus) ifp_iis_ws 47 ifp word select output for external dsp ic enabled by ifp_iis_en (i 2 s-bus) scl 48 serial clock input (i 2 c-bus) sda 49 serial data input/output (i 2 c-bus) rds_clk2 50 rds2 bit clock input/output; default input enabled by rds2_clkin rds_data2 51 rds2 data output of rds2 demodulator rds_clk1_davn2 52 davn2 or rds1 bit clock input/output; default input enabled by rds1_clkin rds_data1_davn1 53 rds1 data output of rds1 demodulator or rds1 decoder davn1 dsp_io0 54 general purpose input/output for epics (f0 of status register) dsp_io1 55 general purpose input/output for epics (f1 of status register) dsp_io2 56 general purpose input/output for epics (f2 of status register) dsp_io3 57 general purpose input/output for epics (f3 of status register) v ss(i/o4) 58 ground supply 4 for external digital ports dsp_io4 59 general purpose input/output for epics (f4 of status register) dsp_io5 60 general purpose input/output for epics (f5 of status register) dsp_io6 61 general purpose input/output for epics (f6 of status register) dsp_io7 62 general purpose input/output for epics (f7 of status register) dsp_io8 63 general purpose input/output for epics (f8 of status register) v ssd6 64 ground supply for digital circuitry v ddd1(mem) 65 digital supply voltage 1 for memories (2.5 v) v ssd1 66 digital ground supply 1 v ddd2 67 digital supply voltage 2 (2.5 v) v ssd2 68 digital ground supply 2 v ssd5 69 digital ground supply 5 v ddd3 70 digital supply voltage 3 (2.5 v) v ssd3 71 digital ground supply 3 conreg 72 2.5 v regulator control output febreg 73 2.5 v regulator feedback input gapreg 74 band gap reference decoupling pin for voltage regulator v ss(osc) 75 ground supply for crystal oscillator circuitry osc_in 76 crystal oscillator input: local crystal oscillator sense for gain control or forced input in slave mode symbol pin description
2003 nov 18 10 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H osc_out 77 crystal oscillator output: drive output to crystal v dd(osc) 78 positive supply voltage for crystal oscillator circuitry v ss(if) 79 if_ad ground supply vrefif 80 if_ad reference voltage output v dd(if) 81 if_ad 2.5 v supply voltage if_in1 82 analog input to if_ad1 from tuner if output if_vg 83 if_ad virtual ground if_in2 84 analog input to if_ad2 from tuner if output ifss1 85 analog ifss1 input to auxad_1 ifss2 86 analog ifss2 input to auxad_2 ain1_l 87 analog input 1 to aad for left input buffer signal ain1_ref 88 common reference voltage input for ain1 input buffer ain1_r 89 analog input 1 to aad for right input buffer signal v dda1 90 analog supply voltage 1 for auxad and aad analog circuitry (2.5 v) vadcp 91 positive reference voltage input for aad vadcn 92 ground reference voltage input for aad vrefad 93 common mode reference voltage output for aad, auxad and buffers ain2_l 94 analog input 2 to aad for left input buffer signal ain2_ref 95 common reference voltage input for ain2 input buffer ain2_r 96 analog input 2 to aad for right input buffer signal adiff_lp 97 analog input to aad for left positive differential signal adiff_ln 98 analog input to aad for left negative differential signal adiff_rp 99 analog input to aad for right positive differential signal adiff_rn 100 analog input to aad for right negative differential signal symbol pin description
2003 nov 18 11 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 2 application requirements and padcell type per pin symbol pin digital i/o levels application digital function pin state after reset hysteresis required internal pull-down cell name (1) v dd(reg) 1 --- -- vddco mono1_p 2 --- -- apio mono1_n 3 --- -- apio mono2_p 4 --- -- apio mono2_n 5 --- -- apio rrv 6 --- -- apio lrv 7 --- -- apio vdacn 8 --- -- vssco v dda2 9 --- -- vddco vdacp 10 --- -- vddco rfv 11 --- -- apio lfv 12 --- -- apio a0 13 0 to 5 v dc tolerant input - yes pull-down ipthdt5v spdif1 14 --- -- apio spdif2 15 --- -- apio reset 16 0 to 5 v dc tolerant input input yes pull-down ipthdt5v tscan 17 0 to 5 v dc tolerant input input yes pull-down ipthdt5v shtcb 18 0 to 5 v dc tolerant input input yes pull-down ipthdt5v r tcb 19 0 to 5 v dc tolerant input input yes pull-down ipthdt5v ext_iis_ws1 20 0 to 5 v dc tolerant input input yes pull-down ipthdt5v ext_iis_bck1 21 0 to 5 v dc tolerant input input yes pull-down ipthdt5v ext_iis_io1 22 0 to 5 v dc tolerant bi-directional input yes pull-down bpts10tht5v ext_iis_ws2 23 0 to 5 v dc tolerant input input yes pull-down ipthdt5v ext_iis_bck2 24 0 to 5 v dc tolerant input input yes pull-down ipthdt5v ext_iis_io2 25 0 to 5 v dc tolerant bi-directional input yes pull-down bpts10tht5v v ss(i/o1) 26 --- -- vsse3v3 iis_in1 27 0 to 3.3 v dc input input yes pull-down bpt4mthd iis_in2 28 0 to 3.3 v dc input input yes pull-down bpt4mthd iis_in3 29 0 to 3.3 v dc input input yes pull-down bpt4mthd
2003 nov 18 12 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... iis_out1 30 0 to 3.3 v dc output output and low level -- ops10c iis_out2 31 0 to 3.3 v dc output output and low level -- ops10c iis_out3 32 0 to 3.3 v dc output output and low level -- ops10c v ss(i/o2) 33 --- -- vsse3v3 v dd(i/o2) 34 --- -- vdde3v3 ifp_iis_out5 35 0 to 3.3 v dc output output and low level -- ops10c iis_bck 36 0 to 3.3 v dc output 3-state -- ot4mc iis_ws 37 0 to 3.3 v dc output 3-state -- ots10c ifp_iis_in1 38 0 to 3.3 v dc input input yes pull-down ipthd ifp_iis_i2o6 39 0 to 3.3 v dc bi-directional input yes pull-down bpts10thd ifp_iis_i3o4 40 0 to 3.3 v dc bi-directional input yes pull-down bpts10thd ifp_iis_out1 41 0 to 3.3 v dc output output and low level -- ops10c ifp_iis_out2 42 0 to 3.3 v dc output output and low level -- ops10c ifp_iis_out3 43 0 to 3.3 v dc output output and low level -- ops10c v dd(i/o3) 44 --- -- vdde3v3 v ss(i/o3) 45 --- -- vsse3v3 ifp_iis_bck 46 0 to 3.3 v dc output 3-state -- ot4mc ifp_iis_ws 47 0 to 3.3 v dc output 3-state -- ots10c scl 48 0 to 5 v dc tolerant input input yes - iptht5v sda 49 0 to 5 v dc tolerant bi-directional input -- iic400kt5v rds_clk2 50 0 to 5 v dc tolerant bi-directional input yes - bptons10tht5v rds_data2 51 0 to 5 v dc tolerant output output mode (level depends on rds data) -- bptons10tht5v rds_clk1_davn2 52 0 to 5 v dc tolerant bi-directional input yes bptons10tht5v rds_data1_davn1 53 0 to 5 v dc tolerant output output mode (level depends on rds data) -- bptons10tht5v dsp_io0 54 0 to 5 v dc tolerant bi-directional input yes - bptons10tht5v dsp_io1 55 0 to 5 v dc tolerant bi-directional input yes - bptons10tht5v dsp_io2 56 0 to 5 v dc tolerant bi-directional input yes - bptons10tht5v symbol pin digital i/o levels application digital function pin state after reset hysteresis required internal pull-down cell name (1)
2003 nov 18 13 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... dsp_io3 57 0 to 5 v dc tolerant bi-directional input yes - bptons10tht5v v ss(i/o4) 58 --- -- vsse3v3 dsp_io4 59 0 to 5 v dc tolerant bi-directional input yes - bptons10tht5v dsp_io5 60 0 to 5 v dc tolerant bi-directional input yes - bptons10tht5v dsp_io6 61 0 to 5 v dc tolerant bi-directional input yes - bptons10tht5v dsp_io7 62 0 to 5 v dc tolerant bi-directional input yes - bptons10tht5v dsp_io8 63 0 to 5 v dc tolerant bi-directional input yes - bptons10tht5v v ssd6 64 --- -- vssis v ddd1(mem) 65 --- -- vddco v ssd1 66 --- -- vssis v ddd2 67 --- -- vddi v ssd2 68 --- -- vssis v ssd5 69 --- -- vssis v ddd3 70 --- -- vddi v ssd3 71 --- -- vssis conreg 72 --- -- apio febreg 73 --- -- apio gapreg 74 --- -- apio v ss(osc) 75 --- -- vssco osc_in 76 --- -- apio osc_out 77 --- -- apio v dd(osc) 78 --- -- vddco v ss(if) 79 --- -- vssco vrefif 80 --- -- apio v dd(if) 81 --- -- vddco if_in1 82 --- -- aprf if_vg 83 --- -- apio if_in2 84 --- -- aprf ifss1 85 --- -- apio ifss2 86 --- -- apio symbol pin digital i/o levels application digital function pin state after reset hysteresis required internal pull-down cell name (1)
2003 nov 18 14 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... note 1. see table 3. ain1_l 87 --- -- apio ain1_ref 88 --- -- apio ain1_r 89 --- -- apio v dda1 90 --- -- vddco vadcp 91 --- -- apio vadcn 92 --- -- apio vrefad 93 --- -- apio ain2_l 94 --- -- apio ain2_ref 95 --- -- apio ain2_r 96 --- -- apio adiff_lp 97 --- -- apio adiff_ln 98 --- -- apio adiff_rp 99 --- -- apio adiff_rn 100 --- -- apio symbol pin digital i/o levels application digital function pin state after reset hysteresis required internal pull-down cell name (1)
2003 nov 18 15 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H table 3 used padcells and functional speci?cation; notes 1 and 2 notes 1. all pull-down inputs or disabled i/os with pull-down, may be left open-circuit. internally the logic level is guaranteed low, but the pull-down doesnt behave as a normal resistor seen at the pin itself. 2. 5 v tolerant means that the input or 3-stated/disabled output is functioning correctly and will not be damaged when applying externally 5 v, and can thus be used in a normal application. the tolerances of the 5 v are given in the limiting values; see chapter 7. padcell name library name functional specification inputs ipthd iolib_nlm input pad; hysteresis; pull-down; ttl levels iptht5v iolib_nlm_danger input pad; hysteresis; ttl levels; 5 v tolerant ipthdt5v iolib_nlm_danger input pad; hysteresis; pull-down; ttl levels; 5 v tolerant outputs ot4mc iolib_nlm output; 3-state; 4 ma ops10c iolib_nlm output plain; 10 ns slew rate ots10c iolib_nlm output; 3-state; 10 ns slew rate i/os iic400kt5v iolib_nlm_danger input/output; 400 khz i 2 c-bus special cell; 5 v tolerant bpt4mthd iolib_nlm input/output; 4 ma; hysteresis; pull-down; ttl input levels bpts10thd iolib_nlm input/output; 10 ns slew rate; hysteresis; pull-down; ttl input levels bpts10tht5v iolib_nlm_danger input/output; 10 ns slew rate; hysteresis; ttl input levels; 5 v tolerant bptons10tht5v iolib_nlm_danger input/output; open-drain n-channel; 10 ns slew rate; hysteresis; ttl input levels; 5 v tolerant special apio iolib_nlm analog pad input or output aprf iolib_nlm analog high frequency pad input or output supply vddco iolib_nlm v dd core only supply; not connected to internal supply ring vssco iolib_nlm v ss core only supply; not connected to internal supply ring vddi iolib_nlm v dd core supply; connected to internal supply ring vssis iolib_nlm v ss core supply; connected to internal supply ring and substrate vdde3v3 iolib_nlm v dd supply peripheral only vsse3v3 iolib_nlm v ss supply peripheral only
2003 nov 18 16 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H handbook, full pagewidth 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 vrefif v ss(if) v dd(osc) osc_out osc_in v ss(osc) gapreg febreg conreg v ssd3 v ddd3 v ssd5 v ssd2 v ddd2 v ssd1 v ddd1(mem) v ssd6 dsp_io8 dsp_io7 dsp_io6 dsp_io5 dsp_io4 v ss(i/o4) dsp_io3 dsp_io2 dsp_io1 dsp_io0 rds_data1_davn1 rds_clk1_davn2 rds_data2 v dd(reg) mono1_p mono1_n mono2_p mono2_n rrv lrv vdacn v dda2 vdacp rfv lfv a0 spdif1 spdif2 reset tscan shtcb rtcb ext_iis_ws1 ext_iis_bck1 ext_iis_io1 ext_iis_ws2 ext_iis_bck2 ext_iis_io2 v ss(i/o1) iis_in1 iis_in2 iis_in3 iis_out1 iis_out2 iis_out3 v ss(i/o2) v dd(i/o2) ifp_iis_out5 iis_bck iis_ws ifp_iis_in1 ifp_iis_i2o6 ifp_iis_i3o4 ifp_iis_out1 ifp_iis_out2 ifp_iis_out3 v dd(i/o3) v ss(i/o3) ifp_iis_bck ifp_iis_ws scl sda rds_clk2 adiff_rn adiff_rp adiff_ln adiff_lp ain2_r ain2_ref ain2_l vrefad vadcn vadcp v dda1 ain1_r ain1_ref ain1_l ifss2 ifss1 if_in2 if_vg if_in1 v dd(if) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 mgw193 SAA7724H fig.4 pin configuration.
2003 nov 18 17 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 6 functional description 6.1 voltage regulator a voltage regulator (see fig.5) controls all 2.5 v supplies of the chip (see fig.6). the input supply voltage is 3.3 v. an external pmos power transistor (e.g. bsh207) is used to handle power. the regulated 2.5 v supply is derived from a band gap voltage, which is ac-decoupled by an external capacitor. handbook, full pagewidth mgw195 1 m f band gap bsh207 external pmos external decoupling r1 v gap v ss conreg febreg gapreg v dd(reg) r2 on-chip off-chip 72 73 74 1 fig.5 voltage regulator schematic diagram.
2003 nov 18 18 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H handbook, full pagewidth mgw196 1 m h 1 m h 1 m f 1 m f 10 m f 100 nf 3.3 v 2.5 v v ss v ddd3 v ddd2 v ddd1(mem) v dd(osc) v dd(if) v dda1 v dda2 conreg febreg gapreg v dd(i/o2) v dd(i/o3) v dd(reg) bsh207 1 m h off-chip on-chip 70 67 65 78 81 90 9 72 73 74 34 44 1 fig.6 voltage regulator connection diagram.
2003 nov 18 19 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 6.2 audio analog front-end the analog front-end consists of two identical 3rd-order sigma delta stereo adcs (adc1 and adc2) with several input control blocks for handling common mode signals and acting as input selector (see fig.7). handbook, full pagewidth mgw197 int ref cmrr mono2_p vrefad ain1_ref ain2_ref mono2_n mono1_p ifss2 ifss1 mono1_n clkadc1 audioad_1 stereo aic1[1:0] intref1 = 0 refc1 aic2[1:0] aic3[1:0] s1 adf1_2 intref2 = 0 refc2 00 01 10 11 00 01 10 11 00 01 10 11 0 1 s2 0 1 0 1 0 1 1 0 cmrr auxad_2 auxad_1 adiff_r (p/n) adiff_l (p/n) 2 2 ain1_r ain2_r ain1_l ain2_l left2 right2 clkaux auxo2 mixc mix auxo1 audioad_2 stereo 00 01 10 11 00 01 10 11 0 1 clkadc2 0 1 0 1 0 1 volmix[1:0] volmix[5:2] located in sdac aad SAA7724H adf1_1 left1 right1 86 85 2 3 4 5 95 88 93 97, 98 99, 100 96 89 94 87 fig.7 analog front-end switch diagram.
2003 nov 18 20 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H the inputs adiff, ain1, ain2, mono1 and mono2 can be selected with the audio input controls (aic1 and aic2). the ground reference (ref1 and ref2) can be selected (refc1 and refc2) to enable the handling of common mode signals for ain1 and ain2. the switches s1 and s2 are needed for handling fully differential inputs at the adiff pins. the mono1 and mono2 inputs have their own cmrr input stage and can be redirected to adc1 and/or adc2 via the audio input control (aic1 and aic2). in this event, the ground reference should be switched to internal (intref = 1). it is also possible to pass mono1/mono2 to the auxad (controlled by aic3) or directly mix the same mono input with four dac output channels, incorporating volume control. 6.2.1 s elector diagram three bits are available to make it possible to redirect the inputs with their corresponding reference to the required audioad (see tables 4 and 5). the input control for the auxad_2 is given in table 6. the input selection of the mixer is given in table 7. table 4 reference connection for audioad_1 and audioad_2 table 5 input connection for audioad_1 and audioad_2 table 6 input connection for auxad_2 table 7 input connection for the mixer i 2 c-bus bit reference connection for audioad_1 and audioad_2 refc1, refc2 intref1, intref2 s1, s2 0 0 0 ref1 1 0 0 ref2 - 1 0 vrefad -- 1 differential i 2 c-bus bit preferred reference input connection for audioad_1 and audioad_2 aic1[1], aic2[1] aic1[0], aic2[0] 0 0 ref1 ain1 0 1 ref2 ain2 1 0 differential adiff 1 1 vrefad mono1 and mono2 i 2 c-bus bit input connection for auxad_2 aic3[1] aic3[0] 0 0 mono1 0 1 mono2 1 0 not connected 1 1 ifss2 i 2 c-bus bit input connection for the mixer mixc 0 mono1 1 mono2
2003 nov 18 21 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 6.2.2 r ealization of the common mode input with ain a high cmrr can be created by the use of ref1 and ref2. these pins can be connected to the positive input of the second operational amplifier in the signal path with bits intref1, intref2, refc1 and refc2 (see fig.8). the signal (of which a high cmrr is required) has a signal and a common signal as input. the common signal is connected to pin ref1 and/or ref2 and can be selected with bits refc1 and/or refc2. the actual input can be selected with the audio input control (bits aic1[1:0] and aic2[1:0]). in fig.8 the ain1 input is selected. in this situation both signal lines going to the adc will contain the common mode signal. the adc itself will suppress this common mode signal with a high rejection ratio. the input pins ain1_l and ain1_r are connected directly to the source. the 1 m w resistor provides the dc biasing of oa3 and oa4. the impedance level, in combination with the parasitic capacitance at input pin ain_l or ain_r, greatly determines the achievable common rejection ratio. handbook, full pagewidth mgw198 60 k w 60 k w 1 m w 10 k w 10 k w ain1_l ain1_r ain1_ref vrefad cd player left ground cd player cable oa1 midref off-chip on-chip 1 0 10 k w oa3 to ad aic1[1:0] = 00 s1 = 0 intref1 = 0 refc1 = 0 1 0 0 1 1 0 11 10 01 00 cd player left 10 k w 10 k w oa2 10 k w oa4 to ad 00 01 10 11 87 89 88 93 fig.8 example of the use of common mode analog input ain1.
2003 nov 18 22 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 6.2.3 r ealization of the differential adiff input the adiff input is fully differential. the signal that is connected to this input should be a symmetrical signal. besides bits aic1[1:0] and aic2[1:0], to select the adiff_l and adiff_r input, the switches s1 and s2 are needed to put the adiff_l and adiff_r inputs in true differential mode (see fig.9). handbook, full pagewidth mgw199 10 k w 10 k w adiff_rp ain1_ref vrefad oa1 midref 1 0 10 k w oa3 to ad aic1[1:0] = 10 s1 = 1 intref1 = 0 refc1 = 0 1 0 0 1 1 0 11 10 01 00 10 k w 10 k w oa2 10 k w oa4 to ad 00 01 10 11 adiff_rn adiff_lp adiff_ln 99 88 93 100 97 98 off-chip on-chip fig.9 example of the use of differential analog input adiff_l and adiff_r.
2003 nov 18 23 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 6.2.4 r ealization of the auxiliary input with volume control a common mode input with volume control for mixing with four dac outputs is provided (see fig.10). the inputs consist of pins mono1_p and mono2_p, both accompanied with their ground signals (pins mono1_n and mono2_n). after selection of mono1 or mono2, with bit mixc, the volume can be changed from 0to - 22.5 db in 1.5 db steps. the attenuated signal can be added to the left and/or right front and/or left and/or right rear dac channels. when the mix signal is added to the output, the gain of the output is automatically adjusted to prevent clipping at high input levels. the inverse output signal of both cmrr circuits can also be switched to the audioad_1 and/or audioad_2 and/or auxad_2. handbook, full pagewidth mgw200 r = 60 k w volmix[5:2] volmix[5:2] rlm = 1 rrm = 1 flm = 1 frm = 1 volmix[1:0] r audioad_1 or audioad_2 or auxad_2 audioad_1 or audioad_2 or auxad_2 mixc midref mono1_p mono1_n r r r r mono2_p mono2_n vrefad r 0 1 r r volmix[5:2] volmix[5:2] on-chip off-chip 2 3 4 5 93 fig.10 mono input circuit. table 8 mix volume control the bits volmix[5:2] are binary weighted organized and used for setting the mixer gain from 0 to - 18 db. the selection bits are connected to the mixer in the qsdac. i 2 c-bus bit output mix gain (db) volmix[5:0] (hex) 3f 0 3b - 1.5 37 - 3.0 33 - 4.5 2f - 6.0 2b - 7.5 27 - 9.0 23 - 10.5 1f - 12.0 1b - 13.5 17 - 15.0 13 - 16.5 0f - 18.0 0e - 19.5 0d - 21.0 0c - 22.5 00 mute i 2 c-bus bit output mix gain (db) volmix[5:0] (hex)
2003 nov 18 24 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H the bits volmix[1:0] are also binary weighted organized and connected to the analog front-end. the mix signal can be added to all outputs independant of each other. table 9 mix output control; note 1 note 1. x = not controlled by this bit. 6.2.5 s upplies and references 6.2.5.1 reference pins vadcn and vadcp these pins are used as a negative and positive reference for the audioad_1 and audioad_2 and the level adc. these references needs to be clean. 6.2.5.2 reference pin vrefad the midref voltage of the adcs is filtered via this pin. this midref voltage is used for half supply reference of the adcs. external capacitors (connected to groundplane) prevent crosstalk between the switched capacitor dacs of the internal adcs and buffers and improves the power supply rejection ratio of all components (see fig.11). 6.2.5.3 analog supply inputs the analog input circuit has separate power supply (v dda1 ) connections to allow maximum filtering. the input stage of every operational amplifier within the analog front-end is supplied by a 3.3 v supply voltage so as to enable a rail-to-rail input signal. i 2 c-bus bit dac output bit value fl fr rl rr ?m 0 off x x x 1 onxxx frm 0 x off x x 1xonxx rlm 0 x x off x 1xxonx rrm 0 x x x off 1 xxxon v vrefad v vadcp v vadcn C 2 --------------------------------------------- - = handbook, halfpage mgw201 vadcp vrefad vadcn fig.11 vrefad reference circuit.
2003 nov 18 25 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 6.3 ad decimation paths (dad) the ad decimation paths for both the level and audio are achieved in the dad block; (see fig.12). there are two dad blocks implemented for the SAA7724H. the dad block consists of a level decimation filter (ldf) which handles the aux decimation and an audio decimation filter (adf) which handles the audio decimation. handbook, full pagewidth mgw202 cead block 1-bit code filter cead interface controller adf ldf aux(n) _sel_lev_voice ch(n) _dc_offset 1-bit code filter fig.12 dad block diagram. (n) is 1 or 2. 6.3.1 ldf and aux decimation path the input signal has a sample frequency of 128 f s and comes from a 1st-order adc. the first part of the decimation is done using a cic filter. for the aux decimating filter a 2nd-order cic filter is implemented. a branch is also available from this filter for a signal having a sample frequency of 8 f s . this signal also passes a built-in high-pass filter section to make it adequate for level iac detection purposes. with a sampling frequency of 8 42.1875 khz the - 3 db point of this filter is at approximately 60 khz. the cic filter decimates the sample frequency by 64. the new output sample rate is 2 f s . the roll-off of the cic filter needs to be compensated for, therefore, a roll-off compensation filter is utilized. the last stage of the aux decimation filter is the realization of the appropriate bandwidth characteristic. the bits aux1_sel_lev_voice and aux2_sel_lev_voice selects between the level characteristic and the audio characteristic for voice input. the transfer characteristics, level and audio, of the aux decimation filter are illustrated in fig.13. it should be noted that the figure corresponds with a 38 khz sample rate. for the SAA7724H a 42.1875 khz sample rate is used, the horizontal values need to be scaled with a factor of remark : the absolute gain or attenuation of the graphs in fig.13 has no meaning. the relative levels however have. when bit aux1_sel_lev_voice or aux2_sel_lev_voice is logic 1, the coefficient for audio processing is active. when bit aux1_sel_lev_voice or aux2_sel_lev_voice is logic 0, the coefficient for level processing is selected. x sin x ----------- 42.1875 38 ---------------------
2003 nov 18 26 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H handbook, full pagewidth mgw203 70000 80000 f (hz) g (db) 60000 50000 40000 30000 20000 10000 0 - 80 - 40 0 40 80 - 80 - 40 0 40 80 level characteristic audio characteristic fig.13 aux decimation path transfer characteristics. 6.3.2 adf and audio decimation path the input signal has a sample frequency of 128 f s and comes from a third order sigma delta adc. the first step in the decimation process is done by the 1-bit code (cic) filter. this cic filter decimates the input sample rate by a factor of 16, which results in a sample rate of 8 f s . after the 1-bit code filter, sample rehashing is necessary prior to entering the cead block. the cead block decimates the audio samples further by a factor of 8, resulting in a sample rate of 1 f s . the overall gain in the pass-band of the decimation filter, including the cic filter and cead block becomes 4.85 db. a nominal input level of - 7.36 db coming from the adc will result in a - 2.5 db level after decimation. the dc filter in the cead block is controlled by i 2 c-bus bit ch1_dc_offset or ch2_dc_offset; see table 27. there is no power-on reset circuitry implemented. this means that after power-up, all filters will go through a fast transient phase before they reach their steady state behaviour. 6.4 digital audio input/output this section describes the external i 2 s-bus input/output ports, the epics host i 2 s-bus port and the spdif inputs. 6.4.1 g eneral there are two external i 2 s-bus input/output ports available on the circuit, and three host i 2 s-bus ports. the i 2 s-bus inputs and host i 2 s-bus outputs are capable of handling philips i 2 s-bus, and lsb-justified formats of 16, 18, 20 and 24-bit word sizes. the external i 2 s-bus output ports only support philips i 2 s-bus. for the general waveforms of the five possible formats see fig.14. more general information on the philips i 2 s-bus format is given in chapter 12. note: when the applied word length is smaller than 24 bits, the lsb bits will get (internally) a zero value. when the applied word length exceeds 24 bits, the lsbs are skipped.
2003 nov 18 27 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth mgw204 16 b5 b6 b7 b8 b9 b10 left lsb-justified format 24 bits ws bck data right 15 18 17 20 19 22 21 23 24 2 1 b3 b4 msb b2 b23 lsb 16 b5 b6 b7 b8 b9 b10 15 18 17 20 19 22 21 23 24 21 b3 b4 msb b2 b23 lsb 16 msb b2 b3 b4 b5 b6 left lsb-justified format 20 bits ws bck data right 15 18 17 20 19 2 1 b19 lsb 16 msb b2 b3 b4 b5 b6 15 18 17 20 19 2 1 b19 lsb 16 msb b2 b3 b4 left lsb-justified format 18 bits ws bck data right 15 18 17 2 1 msb b2 b3 b4 b17 lsb 16 15 18 17 2 1 b17 lsb 16 msb b2 left lsb-justified format 16 bits ws bck data right 15 2 1 b15 lsb 16 msb b2 15 2 1 b15 lsb msb msb b2 2 1 > = 8 12 3 left input format i 2 s-bus ws bck data right 3 > = 8 msb b2 fig.14 waveforms of standardized digital input and output signals.
2003 nov 18 28 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 6.4.2 e xternal i 2 s- bus input / output ports an i 2 s-bus interface is provided for communication with external digital sources. it is a serial 3-line bus, having one line for data, one line for clock and one line for the word select. for external digital sources the circuit acts as a slave, so the external source is master and supplies the bit clock (bck) and word select (ws). figure 15 shows the external i 2 s-bus receiver and controls. table 10 defines the possible modes that must be set for the i 2 s-bus inputs. an extra function that is provided is that the ext_iis ports can also be set, as an output, from the sample rate converters (src). in this event only the philips i 2 s-bus format is supported. table 10 external i 2 s-bus input formats note 1. x = dont care. 6.4.2.1 src audio signal ?ows figure 16 shows the audio signal flow possibilities for the sample rate converters src1 and src2. the inputs to the srcs can be either an external source, or an internal signal from the audio_epics. the outputs from the srcs can either work as a slave output from an externally connected bus to an external i 2 s-bus port 1 or 2, or it can convert the internal SAA7724H sample rate directly to the audio_epics and the switchboard in the ifp. if conversion to an external sample rate is selected, the audio signals to the ifps switchboard and the audio_epics are muted, while their sample rates are maintained at the internal SAA7724H sample rate. all i/o possibilities of the srcs can be set by eight independent i 2 c-bus bits. some selections are conflicting or make no sense. in order to keep as much flexibility as possible there is no detection of conflicting settings, however the circuitry is guaranteed not to cause a hang-up situation. all audio paths to and from the srcs are 24 bits wide. inside the switchboard from the ifp, the audio is always truncated to 16 bits. ext_host_io_format1 [2:0] ext_host_io_format2 [2:0] format 0x (1) x (1) philips i 2 s-bus 1 0 0 lsb -justi?ed 16 bits 1 0 1 lsb-justi?ed 18 bits 1 1 0 lsb-justi?ed 20 bits 1 1 1 lsb-justi?ed 24 bits handbook, halfpage mgw205 ext_iis_w s(n) ext_host_io_forma t(n)[2:0] to src 3 i 2 s-bus receiver ext_iis_bc k(n) ext_iis_dat a(n) fig.15 external i 2 s-bus input and controls. (n) is 1 or 2.
2003 nov 18 29 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H fig.16 src audio signal flows. handbook, full pagewidth mgw206 src1_int_ext_in sel_spdif1_iis1 src2_int_ext_in src1_int_ext_out src1_ext_sel_out src2_ext_sel_out src2_int_ext_out sel_spdif2_iis2 spdif1 in1 in1 out1 in2 out2 in2 src1 audio_epics ifp_swb src2 out2 out1 spdif2 ext_iis_io1 ext_iis_io1 ext_iis_io2 ext_iis_io1 ext_iis_io2 ext_iis_io2 14 15 22 25 25 22 25 22 6.4.2.2 sampling frequency range limitations the external i 2 s-bus inputs are guaranteed for a continuous 8 khz to 48 khz sampling frequency range. 6.4.2.3 bck and ws limitations the rate at which the i 2 s-bus receivers decode data available to the system, depends on the ws frequency. for normal application only 1 f s is used. the ws duty cycle does not need to be 50 % for any of the applied formats. the bck is limited to a maximum frequency of 256 f s . the lower limit is defined by the number of bits that are required to be sent. for lsb-justified formats the number of bcks must be at least the number of bits that is selected per channel. 6.4.3 e xternal spdif input a signal can be applied to one or both of the spdif inputs that conforms to the iec 60958 specification. the spdif receivers support spdif audio data up to 24 bits. some channel status bits are also decoded and made available to the system. there is no support for user data decoding, nor availability of the validity bit. figure 17 shows the spdif receiver and its outputs. the exact meaning of the output bits is given in table 30. the spdif inputs do not have any specific control signals.
2003 nov 18 30 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H handbook, full pagewidth mgw207 spdi f(n) _content spdi f(n) lock audio to src spdi f(n) _emphasis spdi f(n)_fs spdi f(n) _accuracy 2 2 spdif receiver channel status bits on chip off chip 14 or 15 fig.17 spdif receiver and its outputs. (n) is 1 or 2. 6.4.3.1 spdif input application diagram figure 18 shows the general set-up for an spdif input for consumer applications. figure 19 shows an example of how to prevent crosstalk from two adjacent spdif inputs, due to the parasitic capacitance from lead finger and bond wires. therefore extra capacitors are added near the pins. handbook, halfpage mgw208 spdif input 75 w 100 pf 100 nf fig.18 general spdif input application. handbook, full pagewidth mgw209 spdif1 leadfinger/bondwire capacitor 75 w 100 pf 100 pf 100 nf spdif2 75 w 100 pf 100 pf 100 nf 14 15 fig.19 example of crosstalk prevention for spdif inputs.
2003 nov 18 31 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 6.4.3.2 sampling frequency range limitations the external spdif input sample rates are 32, 44.1 and 48 khz. the accuracies of the supported standardized sampling frequencies at the spdif inputs meets the requirements of level ii accuracy as specified in iec 60958, being 0.1 %. 6.4.3.3 channel status bits the channel status bits given in table 11 are available from the spdif receiver. the information is taken from the left audio channel. the channel status bits are available in the i 2 c-bus map, where the exact meaning of the bits can also be found; see table 30. table 11 spdif channel status bits 6.4.3.4 lock indicator the spdif receiver has a lock pin. the polarity is described in the i 2 c-bus map. when the system is not in lock, the audio data will be muted (being zero data values). in the event that the spdif signal is missing or very distorted, the timing information to the src from the spdif receiver will not be good or may even disappear. this will cause the src to get unlocked. locking will occur within 5 ms after reset, or 5 ms after the availability of a proper spdif signal at the input. the lock indicator is available at one of the epics status flags, and thus also readable via the i 2 c-bus. the exact location is given in table 25. 6.4.4 epics host i 2 s- bus port because this is a master i/o port the epics host i 2 s-bus generates its own ws and bck. there is one ws and bck for all three output and input data paths. the definition of how the ws and bck are generated can be found in chapter 11. figure 20 shows the epics host i 2 s-bus i/o and controls. the epics host i 2 s-bus has its own setting for selecting the formats; see table 12. the setting of the epics rate should be taken into account, for setting the desired host i 2 s-bus format. the lsb-justified formats 18, 20 and 24 bits are not available when the epics is running at a rate other than 1 f s . channel status bit number consumer format meaning 1 data/audio mode 3 pre-emphasis 25 and 24 sampling frequency 29 and 28 clock accuracy handbook, halfpage 3 mgw210 host_io_format[2:0] to epics from epics i 2 s-bus transceiver iis_in1 iis_in2 iis_in3 iis_out1 iis_out2 iis_out3 iis_ws iis_bck 27 28 29 30 31 32 37 36 off chip on chip fig.20 epics host i 2 s-bus with controls.
2003 nov 18 32 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H table 12 external epics host i 2 s-bus formats notes 1. x = dont care. 2. not supported for epics rates other than 1 f s . 6.5 sample rate converter there are two sample rate converters (srcs) available in the SAA7724H. the input of each src can be an external source or internal audio from the audio_epics. the outputs are fed to the ifps switchboard and the audio_epics or to an external i 2 s-bus port; see section 6.4.2.1. both srcs meet the requirements given in table 13. table 13 src speci?cation host_io_format2 host_io_format1 host_io_format0 format 0x (1) x (1) philips i 2 s-bus 1 0 0 lsb-justi?ed 16 bits 1 0 1 lsb-justi?ed 18 bits; note 2 1 1 0 lsb-justi?ed 20 bits; note 2 1 1 1 lsb-justi?ed 24 bits; note 2 src characteristic specification input sample rate continuously 8 khz to 48 khz; absolute accuracy 0.1 % output sample rate continuously 8 khz to 48 khz thd + n 3 96 db at 1 khz overall gain 0 db maximum ripple amplitude (0 to 0.45 f s ) 0.1 db stop band suppression (0.55 f s to 1 f s ) 3 98 db output word width 24 bits lock time 45 ms audio during unlocked state muted (zero data)
2003 nov 18 33 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 6.6 if_ad the if_ad performs the analog-to-digital conversion of the fm/am-if signal. it generates 10-bit data. for dual radio two if_ad convertors are incorporated (see fig.21). handbook, full pagewidth if_ad1 if_in1 if_in if_ad_out dither_gain dit_in if_ad_out1 dith_gain_1 dit_in1 if_ad_clk if_vg v dd(if) vrefif v ss(if) if_ad2 if_in if_ad_out dither_gain dit_in if_ad_out2 if_ad_clk dith_gain_2 dit_in2 if_ad_clk if_vg v dd(if) vrefif v ss(if) if_in2 if_vg v dd(if) vrefif v ss(if) mgw211 82 84 83 81 80 79 on chip off chip fig.21 if_ad dual block diagram. 6.6.1 if_ad single block diagram the if_ad block diagram shows the analog part. it consists of a buffer and dither block and a two-step adc.
2003 nov 18 34 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 6.6.2 if_ad detailed functional description the if_ad consists of several blocks. these blocks are the adc itself preceded by a buffer and dither differential summing point. the dither is made with a dither dac (dit_dac) combined with gain variation in g_dac. the interface to the ifp is fed via the registers shown in fig.22. handbook, full pagewidth b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 if_ad_out(n) if_ad_clk register two step adc mgw212 dit_dac dit_in(n) if_in(n) v dd(if) v ss(if) if_vg register 4-bit g_dac r1 r1 buffer and dither i g rdit bd0 bd7 r2 234 w 234 w 234 w 234 w dith_gain_(n) 0 3 10 k w 10 k w 10 k w 10 k w off-chip on-chip 82, 84 81 79 83 fig.22 if_ad single block diagram; analog part. (n) is 1 or 2.
2003 nov 18 35 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 6.6.2.1 adc the adc is based on the two-step principle. 6.6.2.2 buffer the buffer is configured as a single-ended to differential convertor. 6.6.2.3 dithering dither can be applied via the dither dacs dit_dac and g_dac. the input voltage range and the dither level are both proportional to the supply voltage. dit_dac is driven by the ifp. the source is an 8-bit word having 9 values representing - 4 (00000000) to +4 (11111111). the total number of 1s in the 8-bit input word represent the code that the dit_dac is using. the maximum negative output voltage is represented by all 0s on the 8-bit word, and the maximum positive output voltage is represented by all 1s on the 8-bit word. a nominal value of 0 v, which is half way between the maximum positive output voltage and the maximum negative output voltage at the output of the dit_dac, is represented by setting any four of the eight bits to logic 1 and the other four bits to logic 0. to adjust the g_dac dither to the required level, the multiplying current of the dit_dac can be changed with a binary weighted current dac. the reference current is derived from an internal reference source which is proportional to v dd(if) . as a reference point for the equivalent input dither level, at nominal supply voltage, the following equation is used: v ditppeq = 3.7 ditgain (mv). 6.7 audio_epics speci?c information this chapter contains specific additional information, over the epics7a programmers guide, specifically for the SAA7724H. the i 2 c-bus registers, some of which are mapped onto xmem address space, are shown in chapter 11.5, tables 21 to 23. 6.7.1 audio_epics start - up the audio_epics will start running the code after the reset procedure has been completed. this code will start running from address 0 by default, if not reprogrammed by the user before releasing the pc_reset bit. 6.7.2 audio_epics memory overview the memory sizes for the audio_epics are given in table 14. table 14 audio_epics memory list 6.8 sdac output path there are two sdacs implemented in the SAA7724H, one for the front channels (sdac_f) and one for the rear channels (sdac_r). the total digital-to-analog conversion path, consists of the following components (see fig.23): 1. an upsample filter 2. a 3rd-order noise shaper 3. a compensation and dynamic element matching (codem) scrambler 4. the multibit sdac with current compensation. all circuitry including the analog part use a 128 f s clock. memory type product version dsp program memory rom: 5120 words dsp x memory ram: 3584 words dsp y memory ram: 1024 words handbook, full pagewidth mgw213 upsample filter noise shaper 1f s 128f s codem 128f s compensation dac multibit dac 1 0 1 0 fig.23 sdac path diagram.
2003 nov 18 36 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 6.8.1 dac upsampling filter the upsampling filter interpolates a 24-bit stereo signal from 1 f s to 8 f s by cascading two half-band fir filters. interpolating to 128 f s is done by a sample-and-hold filter. 6.8.2 dac noise shaper a 3rd-order noise shaper is used to quantize the 24-bit input signal that is fed from the upsampling filter into a 5-bit output signal. the generated quantization noise is shaped outside the audio band. 6.8.3 dac c o dem scrambler the codem scrambler has three different functions. firstly it converts the 5-bit signal from the noise shaper into a thermometer code. secondly, after conversion, the thermometer code is scrambled by means of a dynamic element matching (dem) algorithm. thirdly, by using this code, matching errors in the analog part of the sdac have less influence on the performance. the codem also generates a compensation vector for the compensation part of the dac. 6.8.4 m ulti - bit sdac the sdac is a multi-bit dac based upon 31 switched resistors. the 31 resistors form a network which can create 32 dc output levels. the exact analog output level is the sum of the dc level and the superimposed bitstream signal. in the application a simple low-pass filter (one capacitor) must be used at the outputs of the sdac. the overall dac filters spectral plot is illustrated in fig.24. as an example a left filtered output is selected, which also has a 3.3 nf output filtering capacitor connected. handbook, full pagewidth mgw214 20 filter 100 1 k 10 k 100 k 1 m a (db) 3 m - 200 - 175 - 150 - 125 - 100 - 75 - 50 - 25 0 f (hz) left_filtered fig.24 dac filters spectral diagram. 6.8.5 a nalog summer function the sdac is featured with the analog summing of signals from the adcs; for details of this function see chapter 6.2.
2003 nov 18 37 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 6.8.6 sdac application diagram an example of the circuitry surrounding the dac outputs is illustrated in fig.25. handbook, full pagewidth mgw215 100 m f 100 nf 47 m f 100 nf 89 10 vdacn v dda2 vdacp SAA7724H 3.3 nf rrv 6 47 m f 3.3 nf lrv 7 47 m f 3.3 nf rfv 11 47 m f 3.3 nf lfv 12 47 m f fig.25 dac outputs application diagram. 6.9 reset block functional overview the reset block uses the asynchronous reset signal from pin reset to generate synchronous reset signals. the generated reset signals are described in the following sections. 6.9.1 a synchronous reset the asynchronous reset signal from pin reset asynchronously disables the sda pin (set high) whenever the reset signal is active. furthermore, all 3-state and bidirectional outputs are kept 3-state asynchronously as long as pin reset is kept low, and the internal reset sequence is still ongoing. it requires approximately 1100 oscin_clk cycles to complete the reset sequence after the reset pin has gone high. after reset the state of the SAA7724H will be as specified in table 2. 6.10 clock circuit and oscillator 6.10.1 c ircuit description the chip has an on-board crystal clock oscillator with amplitude control based on a pierce oscillator; see fig.26. the oscillator is implemented as an inverter with capacitive coupling at the input. when the transconductance of this inverter is sufficiently high, the feedback loop becomes unstable and the circuit starts to oscillate. this oscillation grows until its amplitude has reached a specific value which is detected by the agc. in this way, clipping of the output voltage against the supply voltages is prevented. the agc also ensures that the transconductance builds up very rapidly after power-on and stays sufficiently high during oscillation. the sinusoidal output is converted into a cmos compatible clock by the comparator.
2003 nov 18 38 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H handbook, full pagewidth mgw224 100 k w l1 2.2 m h c3 10 nf cx2 15 pf cx1 15 pf v dd(osc) v ss(osc) agc xtal1 on-chip off-chip xtal2 osc_in osc_out clkout gm r bias 76 77 78 75 fig.26 schematic diagram of the crystal oscillator circuit. 6.10.2 e xternal clock input mode it is possible to use the oscillator as a clock input. in external clock input mode, an external clock signal is input on pin osc_in and this clock signal is transferred to the output via an extra output inverter stage. in this mode, the quartz crystal, l1, cx2 and c3 may be removed, but this is not obligatory. 6.10.3 c rystal oscillator supply the power supply connections to the oscillator are separated from the other supply lines to minimize feedback from on-chip ground bounce to the oscillator circuit. noise on the power supply affects the agc operation therefore the power supply should be decoupled. the v ss(osc) pin is used as ground supply and the v dd(osc) as the positive supply. 6.10.4 a pplication guidelines for correct operation of the oscillator, two load capacitors (cx1 and cx2) need to be added externally to the chip. this configuration is adequate for the required crystal frequency of 43.2 mhz. the external components shown in fig.26 are specified in table 15. the use of other values may prevent the oscillator from start-up. a quartz crystal oscillator is used to generate the clock signal clkout. in the case of an overtone oscillator, the ground harmonic is filtered out by l1 and cx2. a quartz crystal should be used with a series resonance resistance of less than 80 w and a capacitance of less than 7 pf. the crystal should be manufactured for a load capacitance of 10 pf. the value of c3 is not critical as long as it is not much lower than 10 nf (10 % is accurate enough). there is no theoretical upper limit. table 15 external components speci?cation for the crystal oscillator component min. typ. max. unit cx1 13.5 15.0 16.5 pf cx2 13.5 15.0 16.5 pf c3 9 10 - nf l1 1.98 2.2 2.42 m h
2003 nov 18 39 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 6.11 pll circuits in the SAA7724H two pll circuits (pll1 and pll2) are available that deliver the clocks for the audio_epics and the src_epics block. 6.12 rds in the SAA7724H there are two rds demodulation and decoder systems available. the description applies to each of the rds blocks. 6.12.1 g eneral description the rds function recovers the additional inaudible rds information which is transmitted by fm radio broadcasting. the operational functions of the demodulator and decoder are in accordance with ebu specification en 50067. the rds function processes the rds signal, that is frequency multiplexed in the stereo-multiplex signal, to recover the information transmitted over the rds data channel. this processing consists of band-pass filtering, rds demodulation and rds/rbds decoding. the stereo-multiplex signal is input from the ifp. under control of i 2 c-bus bit rds_clkin, an internal buffer can be used to read out the raw rds stream in bursts of 16 bits. with the i 2 c-bus bit rds_clkout the rds clock can be enabled or switched off. the rds band signal level can be read from a memory location in the src_epics, which needs to be defined. the rds band-pass filter discards the audio content from the input signal and reduces the bandwidth. the rds band signal level detector removes a possible autofahrer rundfunk information (ari) signal from the rds band-pass filter output and measures the level of the remaining signal. the rds demodulator regenerates the raw rds bitstream (bit rate = 1187.5 hz) from the modulated rds signal in two steps. the first step is the demodulation of the double sideband suppressed carrier signal around 57 khz into a baseband signal, by carrier extraction and down-mixing. the second step is the binary phase shift key (bpsk) demodulation of the biphase coded baseband signal, by clock extraction and correlation. the rds/rbds decoder provides block synchronization, error detection, error correction, complex flywheel function and programmable block data output. newly processed rds/rbds block information is signalled to the main microcontroller as new data available using the davn output. the block data itself and the corresponding status information can be read out via an i 2 c-bus request. the rds/rbds decoder contains the following major functions needed for rds/rbds data processing: rds and rbds block detection error detection and correction fast block synchronization synchronization control (flywheel) mode control for rds/rbds processing different rds/rbds block information output modes (e.g. a/c block output mode). external decoding of the raw rds bitstream, would require a microcontroller interrupt every 842 m s. the double 16-bit rds buffer allows the rds data to be monitored at a 16 times lower rate, i.e. every 13.5 ms.
2003 nov 18 40 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H handbook, full pagewidth mgw216 rds band-pass filter src_epics decoder_bypass_mux demodu- lator 0 1 stereo- mpx bslp bspa davn outmux rdcl rdda rds/rbds decoder (rbds + ) bit buffer rds_buf_mux 01 rds(n) _clkout rds(n) _clk rd s(n) _data rds(n) _clkin fig.27 rds/rbds functional block diagram. (n) is 1 or 2. 6.12.2 rds i/o modes apart from control inputs and data outputs via the i 2 c-bus, the following inputs and outputs are related to the rds function. unbuffered raw rds output mode (rds1_clkin = 0, rds2_clkin = 0, rds1_clkout = 1, rds2_clkout = 1 and davd mode: dac0 = 1 and dac1 = 1): rds_clk: clock of the raw rds bitstream, extracted from the biphase coded baseband signal by the rds demodulator. a clock period of 1.1875 khz and 50 % duty cycle. the positive edge can be used to sample the rds_data output. rds_data: raw rds bitstream, generated by the demodulator detection of a positive going edge on the rdcl input signal. the data output changes every 100 m s (this equals 1 8 of the rds_bck period) after the falling edge of rds_bck. this allows for external receivers of the rds data to clock the data on the rds_bck signal as well as on its inverse. buffered raw rds output mode (rds1_clkin = 1, rds2_clkin = 1, rds1_clkout = 0, rds2_clkout = 0 and davd mode: dac0 = 1 and dac1 = 1): rds_clk: burst clock generated by the microcontroller. bursts of 17 clock cycles are expected. the average time between bursts is 13.5 ms. rds_data: bursts of 16 raw rds bits are output under control of the burst clock input. after a data burst, this output is high. it is pulled low when 16 new bits are made available and a new clock burst is expected. the microcontroller has to monitor this line at least every 13.4 ms. dava, davb and davc modes (rds1_clkin = 0, rds2_clkin = 0, rds1_clkout = 0 and rds2_clkout = 0): davn: data available signal for synchronization of data request between main controller and decoder; see section 6.12.5.11. rds1_clkin = 1, rds2_clkin = 1, rds1_clkout = 1 and rds2_clkout = 1 is a not allowed mode. as shown in fig.27, the same output is used for rds_data and davn, depending on the selected mode. 6.12.3 rds demodulator phase jumps of the extracted rds clock are detected and accumulated. if the accumulated phase shift exceeds a certain threshold, the rds/rbds decoder is informed by the bit slip (bslp) signal. if the rds/rbds decoder
2003 nov 18 41 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H detects a bit slip, the rds demodulator is informed by the bit slip acknowledge (bspa) signal. this causes the accumulation of rds clock phase shifts to be cleared. 6.12.4 rds bit buffer the repetition frequency of rds data is 1187.5 hz. this results in an interrupt on the microcontroller every 842 m s. the double 16-bit buffer enables this timing requirement to be relaxed. the two 16-bit buffers are alternately filled. if a buffer is not read out by the time the other buffer is filled, it will be overwritten and the old data will be lost. when a 16-bit buffer is being filled, the rds bit buffer keeps the data line high. if a 16-bit buffer is full, the data line is pulled down. the microcontroller has to monitor the data line at least every 13.5 ms. the data line remains low until the microcontroller pulls the clock line low. this initiates the reading of the buffer and the first bit is output on the data line. the rds bit buffer outputs a bit on the data line after every falling clock edge. the data is valid when the clock is high. after 16 falling and 16 rising edges, the whole buffer is read out and the bits are stored by the microcontroller. after a 17th falling clock edge, the data line is set high until the other 16-bit buffer is full. the microcontroller stops communication by pulling the clock line high again. 6.12.5 rds/rbds decoder the rds/rbds decoder handles the complete data processing and decoding of the continuously received serial rds/rbds demodulator output data stream (rdda and rdcl). different data processing modes are software controllable by the external main controller via an i 2 c-bus request. all control signals are direct inputs to the decoder and are also available via the i 2 c-bus. processed rds/rbds data blocks with corresponding decoder status information are available via the i 2 c-bus. the output signals of the decoder are direct outputs and available via the i 2 c-bus. the rds/rbds decoder contains the following functions: rbds processing mode rds/rbds block detection error detection and correction synchronization flywheel for synchronization hold bit slip correction data processing control restart of synchronization mode error correction control mode for synchronization data available control modes data output of rds/rbds information. the functions which are realized in the decoder are described in detail in the following sections. 6.12.5.1 rbds processing mode the decoder is suitable for receivers intended for the european (rds) and the usa (rbds) standard. if the rbds mode is selected (rbds = 1) via the i 2 c-bus, the block detection and the error detection and correction are adjusted to rbds data processing; i.e. e blocks are also treated as valid blocks. if rbds is reset to zero then rds mode is selected. 6.12.5.2 rds/rbds block detection the rds/rbds block detection is always active. for a received sequence of 26 data bits, a valid block and corresponding offset are identified using syndrome calculation. during a synchronization search, the syndrome is calculated with every newly received data bit (bit-by-bit) for a received 26-bit sequence. if the decoder is synchronized, syndrome calculation is activated only after 26 data bits for each new block are received. during rbds reception, including the rds block sequences with (a, b, c/c and d) offset, block sequences of 4 blocks with offset e may also be received. if the decoder detects an e-block, this block is marked in the block identification number (blnr[2:0]) and is available via an i 2 c-bus request. in rbds processing mode the block is signalled as valid e-block and in rds processing mode, where only rds blocks are expected, it is signalled as invalid e-block. this information can be used by the main controller to detect e-block sequences and identify rds or rbds transmitter stations. 6.12.5.3 error detection and correction the rds/rbds error detection and correction recognizes and corrects transmission errors within a received block via parity-check in consideration of the offset word of the expected block. burst errors, with a maximum length of 5 bits, are corrected using this method; see table 16.
2003 nov 18 42 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H after synchronization has been detected the error correction is always active, depending on the pre-selected error correction mode for synchronization (mode synca to syncd), but cannot be carried out in every reception situation. during a synchronization search, the error correction is disabled for detection of the first block and is enabled for processing of the second block, depending on the pre-selected error correction mode for synchronization. the processed block of data and the status of error correction are available for data request, via the i 2 c-bus, for the last two blocks. table 16 rds processed error correction processed blocks are characterized as uncorrectable under the following conditions: during a synchronization search; if the burst error (for the second block) is higher than allowed by the pre-selected correction mode synca to syncd after synchronization has been detected; if the burst error exceeds the correctable maximum 5-bit burst error or if errors are detected but error correction is not possible. 6.12.5.4 synchronization the decoder is synchronized if two valid blocks in a valid sequence are detected by the block detector; see figs 8 and 9 for synchronization strategy overview. the search for the first block is done by a bit-by-bit syndrome calculation, starting after the first 26 bits have been received. this bit-by-bit syndrome calculation is carried out until the first valid, and error free, block has been received. the next block is then calculated and syndrome calculation is done after the next 26 bits have been received. the block-span in which the second valid and expected block can be received is selectable via the previous setting of the maximum bad blocks gain (rds2_mbbg[4:0] or rds1_mbbg[4:0]). if the second received block is an invalid block, then the bad_blocks_counter is incremented and the next new block is calculated. if the bad_blocks_counter value reaches the pre-selected max_bad_blocks_gain, then the bit-by-bit search for the first block is restarted. if the rds mode is selected then the next block is always calculated from the sequence a-b-c or c-d, because e blocks are not allowed. if the rbds mode is selected additional e blocks are allowed. however, while the synchronization search is active the block sequence e-e is always invalid (no synchronization will be found with e-e blocks in a row). if the first correctly detected block is block e, then the next expected block is block a; in this case no further expected blocks will be calculated. the decoder waits for an a block until the bad_blocks_counter value reaches the pre-selected max_bad_blocks_gain or a valid a block is received. if the first correct detected block is block d (in rbds mode) then the next expected block will be block a. if the next expected block is block a (in rbds mode) then a valid uncorrected block e is always allowed to be synchronized. if both blocks a and e fail, the next expected block calculated is block b and so on. for the second block, error correction may also be enabled, depending on the pre-selected correction mode synca to syncd. only valid and/or correctable second blocks are accepted for synchronization. if the pre-selected max_bad_blocks_gain value is set to zero, then (in this case only) the two-path synchronization search function is active independent of the selected rds or rbds mode. that is, if the first block was detected as a valid block, then path 1 is open and the next expected block is calculated and stored. with each new received bit (bit-by-bit) syndrome calculation is started again until a second valid block is detected or 26 bits are received. if a second valid block was detected before 26 bits were received, then path 2 is open, the block position (bit counter) is stored and the next expected block for path 2 is calculated. if 26 bits have been received (after the first block path 1) and the syndrome calculation gives the valid expected block for path 1, then synchronization is detected and path 2 is ignored. if 26 bits have been received (after the first block path 1) and the syndrome calculation gives no validity or it is not the expected block for path 1, then path 1 is set to path 2 values (if path 2 is active): bit_count_path1 bit_count_path2 and expected_block_path1 expected_block_path2. path 2 is exb1 exb0 description 0 0 no errors detected 0 1 burst error of maximum 2 bits corrected 1 0 burst error of maximum 5 bits corrected 1 1 uncorrectable block
2003 nov 18 43 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H then cleared and ready for new input, but only after reception of the next few bits (until 26) may synchronization be detected. thus using this path 2 implementation a much faster synchronization is given in cases of wrong block interpretation of the first detected block. if synchronization is detected, the synchronization status flag (sync) is set and available via an i 2 c-bus request. the synchronization is held until the bad_blocks_counter value reaches the pre-selected max_bad_blocks_lose value (used for synchronization hold) or an external restart of synchronization is performed (nwsy = 1 or power-on reset). 6.12.5.5 flywheel for synchronization hold an internal flywheel is implemented to enable a fast detection of loss of synchronization. therefore one counter (bad_blocks_counter) checks the number of uncorrectable blocks and a second counter (good_blocks_counter) checks the number of error free or correctable blocks. error blocks increment the bad_blocks_counter value and valid blocks increment the good_blocks_counter value. if the counter value of the good_blocks_counter reaches the pre-selected max_good_blocks_lose value (mgbl[5:0]) then the good_blocks_counter and bad_blocks_counters are reset to zero. however, if the bad_blocks_counter value reaches the pre-selected max_bad_blocks_lose value (mbbl[5:0]) then a new synchronization search (bit-by-bit) is started (sync = 0) and both counters are reset to zero. the flywheel function is only activated if the decoder is synchronized. the synchronization is held until the bad_blocks_counter value reaches the pre-selected max_bad_blocks_lose value (loss of synchronization) or an external forced start of a new synchronization search (nwsy = 1) is performed. the maximum values for the flywheel counters are both adjustable via the i 2 c-bus in a range of 0 to 63. 6.12.5.6 bit slip correction during poor reception situations phase shifts of one bit to the left or right ( 1-bit slip) between the rds/rbds clock and data may occur, depending on the lock conditions of the demodulators clock regeneration. if the decoder is synchronized and detects a bit slip (bslp = 1), the synchronization is corrected by +1, 0 or - 1 bit via block detection on the respectively shifted expected new block. 6.12.5.7 data processing control the decoder provides different operating modes selectable by the nwsy, sym0, sym1, dac0 and dac1 inputs via the external i 2 c-bus. the data processing control performs the pre-selected operating modes and controls the requested output of the rds/rbds information. 6.12.5.8 restart of synchronization mode the restart synchronization (nwsy) control mode immediately terminates the actual synchronization and restarts a new synchronization search procedure (nwsy = 1). the nwsy flag is automatically reset after the restart of synchronization by the decoder [new synchronization restart (nwsyre pulse)]. this mode is required for a fast new synchronization on the rds/rbds data from a new transmitter station if the tuning frequency is changed by the radio set. restart of a synchronization search is automatically carried out if the internal flywheel signals a loss of synchronization. 6.12.5.9 error correction control mode for synchronization for error correction and identification of valid blocks during a synchronization search and synchronization hold, four different modes can be selected by control mode inputs sym1 and sym0: 1. mode synca (sym1 = 0 and sym0 = 0): no error correction; the blocks that are detected as correctable are treated as invalid blocks, the internal bad_blocks_counter value is still incremented even if correctable errors are detected. if synchronized, only error free blocks increment the good_blocks_counter value. all blocks except error free blocks increment the bad_blocks_counter value. 2. mode syncb (sym1 = 0 and sym0 = 1): error correction of burst error maximum 2 bits; the blocks that are corrected are treated as valid blocks, all other errors detected are treated as invalid blocks. if synchronized, error free and correctable maximum 2-bit errors increment the good_blocks_counter value. 3. mode syncc (sym1 = 1 and sym0 = 0): error correction of burst error maximum 5 bits; the blocks that are corrected are treated as valid blocks, all other errors detected are treated as invalid blocks. if synchronized, error free and correctable maximum 5-bit errors increment the good_blocks_counter value.
2003 nov 18 44 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 4. mode syncd (sym1 = 1 and sym0 = 1): no error correction; the blocks that are detected as correctable are treated as invalid blocks, if in synchronization search mode. the internal bad_blocks_counter value is always incremented even if correctable errors are detected. if synchronized, error free blocks and correctable maximum 5-bit errors increment the good_blocks_counter value. only uncorrectable blocks increment the bad_blocks_counter value. 6.12.5.10 data available control modes the decoder provides three different rds/rbds data output processing modes plus one decoder bypass mode which are selectable via the data available control mode inputs dac1 and dac0. mode dava (dac1 = 0 and dac0 = 0): standard output mode; if the decoder is synchronized and a new block is received (every 26 bits), the actual rds/rbds information of the last two blocks is available with every new received block (approximately every 21.9 ms). mode davb (dac1 = 0 and dac0 = 1): fast pi search mode; during synchronization search and if a new a or c block is received, the actual rds/rbds information of this or the last two a or c blocks respectively is available with every new received a or c block. if the decoder is synchronized, the standard output mode is active. mode davc (dac1 = 1 and dac0 = 0): reduced data request output mode; if the decoder is synchronized and two new blocks are received (every 52 bits), the actual rds/rbds information of the last two blocks is available with every two new received blocks (approximately every 43.8 ms). mode davd (dac1 = 1 and dac0 = 1): decoder bypassed mode; if this mode is selected then the outmux output of the decoder is reset to low (outmux = 0). the madre internal row buffer output is then active and the decoder is bypassed. the decoder provides data output of the block identification of the last and previously processed blocks, the rds/rbds information words and error detection/correction status of the last two blocks together with general decoder status information. in addition the decoder output is controlled indirectly by the data request from the external main controller. the decoder receives a data overflow (dofl) signal controlled by the i 2 c-bus register interface. this dofl signal has to be set high (dofl = 1) if the decoder is synchronized and a new rds/rbds block is received before the previously processed block was completely transmitted via the i 2 c-bus. after detection of data overflow the interface registers are not updated (no decwre) until reset of the data overflow flag (dofl = 0) by reading via the i 2 c-bus or if nwsy = 1 which results in the start of a new synchronization search (sync = 0). 6.12.5.11 data output of rds/rbds information the decoded rds/rbds block information and the current decoder status is available via the i 2 c-bus. for synchronization of data request between the main controller and decoder the additional data available output (davn) is used. for timing information see section 10.1. if the decoder has processed new information for the main controller the data available signal (davn) is activated (low) under the following conditions: during a synchronization search in davb mode if a valid a or c block has been detected. this mode can be used for fast search tuning (detection and comparison of the pi code contained in the a and c blocks). during a synchronization search in any dav mode (except davd mode), if two blocks in the correct sequence have been detected (synchronization criterion fulfilled) if the decoder is synchronized and, in mode dava and davb, a new block has been processed; this mode is the standard data output mode if the decoder is synchronized and, in davc mode, two new blocks have been processed if the decoder is synchronized and, in any dav mode (except davd mode), loss of synchronization is detected (flywheel loss of synchronization, resulting in a restart of the synchronization search) in any dav mode (except davd mode), if a reset caused by power-on or a voltage drop is detected (presn = 0). remark : if the decoder is synchronized, the davn signal is always activated after 21.9 ms in dava or davb mode and after 43.8 ms in davc mode independent of valid or invalid blocks being received. the processed rds/rbds data is available for an i 2 c-bus request for at least 20 ms after the davn signal was activated. the davn signal is always automatically deactivated (high) after ~10 ms or almost after the main controller has read the rds/rbds status byte via the i 2 c-bus (see davn timing).
2003 nov 18 45 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H the decoder ignores new processed rds/rbds blocks if the davn signal is active or if data overflow occurs (dofl = 1). tables 17 and 18 show the block identification number and processed error status outputs of the decoder and how to interpret the output data. table 17 rds block identi?cation number table 18 rds processed error correction 6.12.5.12 power-on reset reset of the chip will cause a number of i 2 c-bus registers to be set to specific default values; see chapter 11.5. if the decoder detects the reset, the status bit reset detected (rstd) is set and available via an i 2 c-bus request. the rstd flag is deactivated after the decoder status register is read by the i 2 c-bus. blnr2 blnr1 blnr0 block identification 000blocka 001blockb 010blockc 011blockd 1 0 0 block c 1 0 1 block e (rbds mode) 1 1 0 invalid block e (rds mode) 1 1 1 invalid block exb1 exb0 description 0 0 no errors detected 0 1 burst error of maximum 2 bits corrected 1 0 burst error of maximum 5 bits corrected 1 1 uncorrectable block
2003 nov 18 46 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 7 limiting values in accordance with the absolute maximum rating system (iec 60134); note 1 notes 1. stresses greater than those listed above may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or at any other condition above those listed in the following recommended operating and characteristics section is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2. not applicable for 5 v tolerant pins. 8 thermal resistance symbol parameter conditions min. typ. max. unit v ddd supply voltage on pin v ddd - 0.5 +2.5 +3.3 v v dd(i/o) supply voltage on pin v dd(i/o) - 0.5 +3.3 +4.2 v v dd(reg) supply voltage on pin v dd(reg) - 0.5 +3.3 +4.2 v v dda supply voltage on pin v dda - 0.5 +2.5 +3.3 v i ddd supply current pin v ddd f c = 43.2 mhz; v ddd = 2.5 v -- 750 ma i ssd supply current pin v ssd f c = 43.2 mhz; v ddd = 2.5 v -- 750 ma i dd(i/o) supply current pin v dd(i/o) f c = 43.2 mhz; v ddd = 3.3 v -- 750 ma i ss(i/o) supply current pin v ss(i/o) f c = 43.2 mhz; v ddd = 3.3 v -- 750 ma i ik dc input clamp diode current v il < - 0.5 v or v ih >v dd(i/o) + 0.5 v; note 2 -- 10 ma v lim(5v) 5 v tolerant pins voltage limits 5 v tolerant outputs: disabled mode - 0.5 - +5.8 v t amb ambient temperature - 40 - +85 c t stg storage temperature - 55 - +150 c v esd electrostatic discharge voltage hbm: 100 pf; 1500 w 2000 -- v mm: 200 pf; 2.5 m h; 15 w 200 -- v i lu(prot) latch-up protection current gqs (snw-fq-611 part e) 100 -- ma symbol parameter condition value unit r th(j-a) thermal resistance from junction to ambient in free air 45 k/w
2003 nov 18 47 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 9 dc characteristics positive current ?ows into the device; 3.13 v v dd(i/o), v dd(reg) 3.47 v; 2.38 v v dda ,v ddd ,v dd(osc), v dd(if) 2.62 v; t amb = - 40 c to +85 c. symbol parameter conditions min. typ. max. unit digital parameters v ddd supply voltage on pin v ddd 2.38 2.5 2.62 v v dd(osc) supply voltage on pin v dd(osc) 2.38 2.5 2.62 v v dd(i/o) supply voltage on pin v dd(i/o) 3.13 3.3 3.47 v v dd(reg) supply voltage on pin v dd(reg) 3.13 3.3 3.47 v i dd(tot) total supply current f osc_in = 43.2 mhz pins v ddd - 215 260 ma pins v dd(i/o) - 510ma pins v dda1 , v dda2 , v dd(if), v dd(osc) - 180 216 ma v ih high-level input voltage v dd(i/o) = 3.3 v; inputs ttl; excluding 5 v tolerant pins 1.7 - 3.3 v v dd(i/o) = 3.3 v; 5 v tolerant inputs ttl; including sda pin 2.0 - 5.5 v v il low-level input voltage inputs ttl; excluding sda pin 0 - 0.7 v 5 v tolerant inputs ttl; including sda pin 0 - 0.8 v v oh high-level output voltage i oh = - 4 ma; v dd(i/o) = 3.3 v 10 ns slew rate outputs 2.9 -- v 4 ma outputs 2.9 -- v v ol low-level output voltage 10 ns slew rate outputs; i ol = 4 ma; v dd(i/o) = 3.3 v -- 0.4 v 4 ma outputs; i ol =4ma -- 0.4 v sda output; i ol = 3 ma; v dd(i/o) = 3.3 v -- 0.4 v i li input leakage current schmitt trigger input without pull-down; excluding 5 v tolerant pins v i =v ss(i/o) --- 1 m a v i =v dd(i/o) -- 1 m a schmitt trigger input without pull-down; 5 v tolerant pins only v i =5v -- 4.5 m a v i =0v --- 4.5 m a
2003 nov 18 48 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H note 1. i dd(q) quiescent device current testing is a proven technique to increase device quality. the testing will be performed in several different logic states, but no guarantee can be given that the current will stay below the specified maximum value in every arbitrary static device state. i ol(z) 3-state leakage current v i =v ss(i/o) ; 3-state outputs without pull-down; excluding 5 v tolerant pins --- 1 m a v i =v dd(i/o) ; 3-state outputs; excluding 5v tolerant pins -- 1 m a v i = 5 v; 3-state outputs and open-drain outputs without pull-down; 5 v tolerant pins only -- 64 m a v hys schmitt trigger hysteresis schmitt trigger inputs; excluding sda pin 0.4 -- v schmitt trigger inputs; 5 v tolerant pins only 0.3 -- v pin sda; v dd(i/o) = 3.3 v 0.15 -- v i dd(q) digital quiescent current v ddd = 2.62 v; v dd(i/o) = 3.47 v; note 1 -- 1ma i i(pd) input pull-down current v dd 2003 nov 18 49 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 10 ac characteristics positive current ?ows into the device; 3.13v v dd(i/o), v dd(reg) 3.47 v; 2.38v v dda ,v ddd ,v dd(osc), v dd(if) 2.62 v; t amb = - 40 c to +85 c. symbol parameter conditions min. typ. max. unit analog inputs d ifferential measurements via audioad_1 and audioad_2; b = 20 k h z psrr power supply rejection ratio v i = 0.1 v (peak); f i = 1 khz 35 -- db a ct cross-talk between pins ain(x) v ain(x) = 0.5 v (rms); f i = 15 khz; adiff(x) path measured --- 70 db pins adiff_lp, adiff_ln, adiff_rp and adiff_rn v i(dif)(rms) differential input voltage (rms value) nominal digital output level - 2.5 db 0.85 1 1.15 v (thd + n)/s total harmonic distortion-plus-noise to signal ratio f i = 1 khz; v i = 1 v (rms) 0 db input level --- 75 db - 60 db input level --- 25 db r i input resistance 45 57 72 k w a cs channel separation v ain(x) = 0.5 v (rms); f i = 15 khz; adiff(x) path measured --- 70 db v o(ub) left and right unbalance v i = 1 v (rms); f i = 1 khz - 0.5 - +0.5 db cmrr common mode rejection ratio f i = 1 khz; v i = 0.1 v 40 -- db cmir common mode input range f i = 1 khz; v i = 0.5 v (rms) 1.0 - 1.5 v f res frequency response f c at - 3db 20 -- khz single - ended measurements via audioad_1 and audioad_2; b = 20 k h z psrr power supply rejection ratio v i = 0.1 v (p); f i = 1 khz 45 -- db pins adiff_lp, adiff_ln, adiff_rp, adiff_rn, ain1_l, ain1_r, ain2_l and ain2_r a ct cross-talk v i = 0.5 v (rms); f i = 15 khz; ain(x) path measured --- 70 db a cs channel separation v i = 0.5 v (rms); f i = 15 khz; ain(x) path measured --- 60 db pins ain1_l, ain1_r, ain2_l and ain2_r v i(rms) input voltage (rms value) nominal digital output level - 2.5 db 0.4 0.5 0.6 v (thd + n)/s total harmonic distortion-plus-noise to signal ratio f i = 1 khz; v i = 0.5 v (rms) 0 db input level --- 75 db - 60 db input level --- 25 db r i input resistance 45 57 72 k w v o(ub) left and right unbalance v i = 0.5 v (rms); f i = 1 khz - 0.5 - +0.5 db cmrr common mode rejection ratio f i = 1 khz; v i = 0.1 v 40 -- db cmir common mode input range f i = 1 khz; v i = 0.5 v (rms) 1.0 - 1.5 v
2003 nov 18 50 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H f res frequency response f c at - 3db 20 -- khz mpx; pins ain1_l, ain2_l adiff_lp and adiff_ln; single - ended and differential inputs measurement via audioad_1 and audioad_2 left (thd + n)/s total harmonic distortion-plus-noise to signal ratio f i = 1 khz; v i = 0.5 v (rms); single-ended; v i = 1 v (rms); differential; b = 40 khz -- 75 - 70 db f i = 1 khz; v i = 0.5 mv (rms); single-ended; v i = 1 mv (rms); differential; b = 40 khz -- 15 - 10 db rds; pins ain1_r, ain2_r adiff_rp and adiff_rn; single - ended and differential inputs measurement via audioad_1 and audioad_2 right (thd + n)/s total harmonic distortion-plus-noise to signal ratio f i = 57 khz; b = 4 khz; v i = 0.5 v (rms); single-ended; v i = 1 v (rms); differential; 0 db input level; reference level = v i --- 65 db f i = 57 khz; b = 4 khz; v i = 0.5 mv (rms); single-ended; v i = 1 mv (rms); differential; - 60 db input level; reference level = v i --- 5db p ins mono1_p, mono1_n, mono2_p and mono2_n; differential measurements via auxad_2 v i(dif)(rms) differential input voltage (rms value) f i = 1 khz; nominal digital output level = - 5db 0.4 0.5 0.6 v (thd + n)/s total harmonic distortion-plus-noise to signal ratio f i = 1 khz; b = 4 khz v i = 0.5 v (rms); 0 db input level --- 45 db v i = 50 mv (rms) --- 35 db psrr power supply rejection ratio amplitude = 0.1 v (p); f i = 1 khz 15 -- db r i input resistance 90 120 150 k w cmrr common mode rejection ratio f i = 1 khz; v i = 0.1 v 40 -- db cmir common mode input range f i = 1 khz 1.0 - 1.5 v f res frequency response f c at - 3db 32 -- khz symbol parameter conditions min. typ. max. unit
2003 nov 18 51 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H p ins mono1_p, mono1_n, mono2_p and mono2_n; differential measurements via audioad_1 and audioad_2 v i(dif)(rms) differential input voltage (rms value) f i = 1 khz; nominal digital output level - 2.5 db 0.4 0.5 0.6 v (thd + n)/s total harmonic distortion-plus-noise to signal ratio f i = 1 khz; b = 4 khz v i = 0.5 v (rms); 0 db input level --- 70 db v i = 0.5 mv (rms); - 60 db input level - - - 25 db psrr power supply rejection ratio v i = 0.1 v (p-p); f i = 1 khz 30 -- db r i input resistance 90 120 150 k w cmrr common mode rejection ratio f i = 1 khz; v i = 0.10 v 40 -- db cmir common mode input range f i = 1 khz 1.0 - 1.5 v f res frequency response f c at - 3db 20 -- khz analog inputs; pins ifss1 and ifss2 single-ended measurements via auxad_1 and auxad_2; b = 32 khz v i input voltage v vadcp - v vadcn = 2.5 v 2.35 2.5 2.65 v v offset offset voltage - 150 +20 +150 mv (thd + n)/s total harmonic distortion-plus-noise to signal ratio f i = 1 khz v i =90% v r (p-p) --- 45 db v i =9% v r (p-p) -- 34 - 28 db r i input resistance f s = 5.4 mhz 500 -- k w f res frequency response f c at - 3db 32 -- khz p ins if_in1, if_in2, if_ad1 and if_ad2 v i(fs)(p-p) full-scale input voltage (peak-to-peak value) nominal digital output level 0db f i = 451 khz 0.82 0.96 1.09 v f i = 10.701 mhz; includes influence of f c(lpf) 0.815 1.04 1.16 v v offset offset voltage adc + buffer + dither - 100 - +100 mv r i input resistance 16 20 24 k w hd am am harmonic distortion - 34 db (fs); measurement with respect to 0 db (fs) f i = 225.500 khz --- 52 db f i = 150.333 khz --- 52 db id am am intermodulation distortion f 1 = 430 khz; - 12 db (fs); f 2 = 411 khz; - 22 db (fs); measurement with respect to 0 db (fs) --- 82 db symbol parameter conditions min. typ. max. unit
2003 nov 18 52 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H hd fm fm harmonic distortion measurement with respect to 0 db (fs) f i = 10.7802 mhz; - 6 db (fs) --- 40 db f i = 5.3505 mhz; - 10 db (fs) --- 44 db f i = 3.567 mhz; - 10 db (fs) --- 44 db f i = 10.833 mhz; - 9 db (fs) --- 66 db id fm fm intermodulation distortion - 12 db (fs); measurement with respect to 0 db (fs); f 1 = 10.833 mhz; f 2 = 10.967 mhz --- 67 db s/n am am signal-to-noise ratio narrow-band f 1 = 451 khz; f 2 = 534.809 khz; v i = 85.3 mv (rms); b = 6 khz; measurement with respect to 0 db (fs); ditgain = 8 83 88 - db s/n fm fm signal-to-noise ratio narrow-band f 1 = 10.701 mhz; f 2 = 10.89255 mhz; v i = 171 mv (rms); b = 180 khz; measurement with respect to 0 db (fs); ditgain = 8 65 72 - db psrr power supply rejection ratio v i = 0.1 v (p); f i = 1 khz 3 6 - db a ct(fm) fm cross-talk f i = 10.701 mhz; amplitude = - 12 db (fs); measurement with respect to 0 db (fs) --- 39 db a ct(am) am cross-talk f i = 451 khz; amplitude = - 12 db (fs); measurement with respect to 0 db (fs) --- 47 db r i(if_vg) input resistance pin if_vg - 400 -w analog if_ad dither dac v dither(p-p) dither level (peak-to-peak) ditgain = 15 56 70 84 mv analog if_ad dither gain dac g step number of gain steps - 16 - g res gain resolution 3.5 4.4 5.3 symbol parameter conditions min. typ. max. unit mv steps ------------- -
2003 nov 18 53 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H dac measurements; 0 db via i 2 s-bus; minimum ac impedance on dac outputs = 100 k w ; ?lter capacitance on dac outputs = 3.3 nf; b = 20 hz to 20 khz, mixer muted psrr power supply rejection ratio pin v dda2 f ripple = 1 khz; v ripple = 0.1 v (p-p); c vdacp =22 m f 36 - db d v dac deviation in output level of the front dac voltage outputs with respect to the average of the front outputs amplitude = 0 db (fs); f i = 1 khz pins rrv and lrv - 0.38 - +0.38 db pins rfv and lfv - 0.38 - +0.38 db p ins rrv, lrv, rfv and lfv m (f-r) matching of the front to rear averages amplitude = 0 db (fs); f i = 1 khz - 0.5 - +0.5 db a ct crosstalk between the four dac output voltages amplitude = 0 db; f i = 1 khz; one output digital silence; three others 0 db (fs); for all combinations -- 70 - 60 db (thd + n)/s total harmonic distortion-plus-noise to signal ratio f i = 1 khz; all four dac outputs driven 0 db (fs); all mixers muted -- 80 - 75 db - 60 db (fs) -- 45 - 40 db 0 db (fs); all mixers on and set to 0 db --- 60 db ds digital silence all zero digital input with respect to 0 db (fs) -- 110 - 105 db v o(dac)(rms) dac output voltage at maximum signal (rms value) ac impedance 3 100 k w ; f i = 1 khz; v dda2 = 2.5 v 0.74 0.75 0.77 v analog mix output; pins rrv, lrv, rfv and lfv thd total harmonic distortion summer input f i = 1 khz; gain setting = 0 db v i = 0.50 v (rms) --- 40 db v i = 0.5 mv (rms) --- 20 db spdif measurements; pins spdif1 and spdif2 v i(p-p) input voltage level (peak-to-peak value) 0.2 0.5 2.5 v r i input resistance - 7 - k w v i(hys) input hysteresis - 30 - mv quartz crystal oscillator measurements; pins osc_in and osc_out; v dd(osc) = 2.5 v; f i = 4 mhz z o(xtal) crystal oscillator output impedance v i = 20 mv (rms) 400 --w g xtal oscillator gain v i = 20 mv (rms) 12 -- ma/v d i xtal oscillator level dependent current difference v i = 20 mv and 200 mv (rms) 2 -- ma symbol parameter conditions min. typ. max. unit
2003 nov 18 54 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H digital output rise and fall times; t amb =25 c; c l =30pf t o(r) output rise time low-to-high transition 10 ns slew rate outputs - 10 - ns 4 ma outputs - 5 - ns t o(f) output fall time high-to-low transition 10 ns slew rate outputs - 10 - ns 4 ma outputs - 5 - ns t o(f)(sda) output fall time high-to-low transition pin sda c b = 10 pf to 400 pf 20 + 0.1c b 250 ns i 2 s-bus inputs and outputs (see fig.29) t cy(bck) i 2 s-bus bit clock cycle time f s = 48 khz; pins ext_iis_bck1 and ext_iis_bck2 81.3 -- ns t s;dat data set-up time pins ext_iis_io1 and ext_iis_io2 10 -- ns pins iis_in1, iis_in2, iis_in3, ifp_iis_in1, ifp_iis_i2o6 and ifp_iis_i3o4 22.9 -- ns t h;dat data hold time pins ext_iis_io1 and ext_iis_io2 5 -- ns pins iis_in1, iis_in2, iis_in3, ifp_iis_in1, ifp_iis_i2o6 and ifp_iis_i3o4 0 -- ns t d;dat data delay time pins iis_out1, iis_out2, iis_out3, ext_iis_ws1, ext_iis_bck1, ext_iis_io1, ext_iis_ws2, ext_iis_bck2 and ext_iis_io2 -- 27 ns t s;ws word select set-up time pins ext_iis_ws1 and ext_iis_ws2 10 -- ns t h;ws word select hold time pins ext_iis_ws1 and ext_iis_ws2 2 -- ns t d;ws word select delay time pins iis_ws1 and ifp_iis_ws -- 27 ns rds inputs and outputs; pins rds_data and rds_bck ; see figs 30 , 31 , 32 and 33 t tdav data valid period dava and davb mode 24.5 26.0 27.0 rds bit periods davc mode 49.0 52.0 54.0 rds bit periods t davnl time data available signal is low dava, davb and davc mode 11.25 12.0 12.5 rds bit periods t sr clock set-up time 100 --m s symbol parameter conditions min. typ. max. unit
2003 nov 18 55 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H t pr period time - 842 -m s t hr clock high time 220 - 640 m s t lr clock low time 220 - 640 m s t dr data hold time 100 --m s t wb wait time (burst mode) 1 --m s t pb period time (burst mode) 2 --m s t hb clock high time (burst mode) 1 --m s t lb clock low time (burst mode) 1 --m s i 2 c-bus inputs and outputs; pins scl and sda; value referenced to v ih minimum and v il maximum levels; see fig.28 f scl scl clock frequency 0 - 400 khz t buf bus free time between a stop and start condition 1.3 --m s t hd;sta hold time (repeated) start condition 0.6 --m s t low low period of the scl clock 1.3 --m s t high high period of the scl clock 0.6 --m s t su;sta set-up time for a repeated start condition 0.6 --m s t hd;dat data hold time 0 - 0.9 m s t su;dat data set-up time 100 -- ns t r rise time of both sda and scl signals c b = total capacitance of one bus line in pf f scl = 400 khz 20 + 0.1c b - 300 ns f scl = 100 khz 20 + 0.1c b - 1000 ns t f fall time of both sda and scl signals c b = total capacitance of one bus line in pf 20 + 0.1c b - 300 ns t su;sto set-up time for stop condition 0.6 --m s c b capacitive load for each bus line -- 400 pf t sp pulse width of spikes which must be suppressed by the input ?lter 0 - 50 ns symbol parameter conditions min. typ. max. unit
2003 nov 18 56 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 10.1 timing diagrams handbook, full pagewidth mbc611 p s sr p t su;sto t sp t hd;sta t su;sta t su;dat t f t high t r t hd;dat t low t hd;sta t buf sda scl fig.28 definition of timing on the i 2 c-bus.
2003 nov 18 57 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H handbook, full pagewidth t s;ws t d;ws t d;dat t s;dat t h;dat t r t bck(h) t bck(l) t f t h;ws left right t cy ws (in) ws (out) data (in) data (out) bck mgw231 fig.29 i 2 s-bus timing diagram for digital audio inputs/outputs. handbook, full pagewidth mgw226 rds_data rds_bck t sr t hr t lr t dr t pr fig.30 rds timing diagram in direct output mode.
2003 nov 18 58 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H handbook, full pagewidth mgw227 t wb t lb t hb t pb rds_data d0 d1 d2 d13 d14 d15 rds_bck fig.31 timing diagram of interface signals between rds function and microcontroller in buffered output mode. handbook, full pagewidth mgw228 davn t davnl t tdav fig.32 rds data available signal (davn); no i 2 c-bus request during davn low time (decoder is synchronized).
2003 nov 18 59 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H handbook, full pagewidth mgw229 i 2 c-bus davn t davnl t tdav r(b)ds status register read fig.33 rds data available signal (davn); davn low timing shorten by data request via i 2 c-bus (decoder is synchronized). 11 i 2 c-bus control general description of the i 2 c-bus format in a booklet can be obtained at philips semiconductors, international marketing and sales. for the external control of the chip a fast i 2 c-bus is implemented. this is a 400 khz bus which is downward compatible with the standard 100 khz bus. there are two different types of control instructions: instructions to control the dsp programs, programming the coefficient ram and reading the values of parameters instructions controlling the data i 2 s-bus flow, like source selection and clock speed. 11.1 i 2 c-bus protocol the bidirectional i 2 c-bus interface acts as a slave transceiver while an external microcontroller acts as a master transceiver. communication between the mpi and the microcontroller is based on the i 2 c-bus protocol. the data transfer on the i 2 c-bus is shown in fig.34. the i 2 c-bus has two lines: a serial clock line scl and a serial data line sda. because the i 2 c-bus is a multi-master bus, arbitration between different master devices is achieved by using a start condition. the master device pulls the open-drain data line low while the clock line remains high. after the bus has been won in this way, data is transmitted serially in packets of 8 bits plus an extra clock pulse for an acknowledgement flag from the receiving device. handbook, full pagewidth mgw217 start data msb data 2 data lsb acknowledge stop 0 6 7 0 ack 6 7 sda scl fig.34 i 2 c-bus interface data transfer sequence.
2003 nov 18 60 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 11.1.1 p rotocol of the i 2 c- bus commands the SAA7724H acts as a slave receiver or slave transmitter; therefore the clock signal is only an input signal. the data signal is a bidirectional open-drain line at the ic pin level. the SAA7724H slave address has a subaddress bit a0 (bit 1) which allows the device to have 1 or 2 different addresses. the least significant bit (bit 0) represents the read/write mode. the read and write i 2 c-bus commands are illustrated in figs 35 to 40, showing sda. the i 2 c-bus interface will generate a negative acknowledge on the sda line in the event that the data transfer was not completed successfully. after generating a start condition, the master device has to transmit a slave address. the slave i 2 c-bus interface responds to its own address (given in the first data byte) by sending an acknowledgement to the master device. the direction flag (bit 0) is always transmitted in this first byte so that the slave knows in which mode it has to operate. initially, the i 2 c-bus interface receives a 16-bit address (2 bytes over the i 2 c-bus) which represents the starting memory address for the data transfer. in the event that a read command is received before the address register has been written, a negative acknowledgement will be generated. in the write mode, the transfer of data words continues until the master device stops the transfer with a stop condition (p). in the read mode, the data transfer continues until a negative acknowledgement and stop condition is generated by the master. in the read mode the last word will not be transmitted to the i 2 c-bus while the i 2 c-bus interface is stopped by the master. when reading from or writing to an invalid address a negative acknowledge will be generated after the first data byte, and the master must then send a stop condition. an acknowledge is generated on all memory locations if selected. also, within a given boundary, an acknowledge will be generated when selected, although the physical size of the memory may not be that large. these are the reserved locations in the i 2 c-bus memory map. a negative acknowledge will only be generated in unused spaces of the i 2 c-bus map. handbook, full pagewidth mhc653 s device w a addrh a a a addrl datah datam a datal a a datah datam a a ...... p datal 0 0 1 1 1 0a0r/w fig.35 write cycle epics (xram). handbook, full pagewidth mhc654 s device w a addrh a a r a addrl device datah a datam a a datal datah a na ...... p 0 0 1 1 1 0a0r/w sr fig.36 read cycle epics (xram).
2003 nov 18 61 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H handbook, full pagewidth mhc655 s device w a addrh a a a addrl datam datal a datam a a datal ...... p 0 0 1 1 1 0a0r/w fig.37 write cycle epics (yram). handbook, full pagewidth mhc656 s device w a addrh a a r a addrl device datam a datal a a datam na ...... p 0 0 1 1 1 0a0r/w sr fig.38 read cycle epics (yram). handbook, full pagewidth mhc657 s device w a addrh a a a addrl datam datal a datam a a datal datam datal aa ...... p 0 0 1 1 1 0a0r/w fig.39 write cycle ifp. handbook, full pagewidth mhc658 s device w a addrh a a r a addrl device datam a datal a a datam datal a na ...... p 0 0 1 1 1 0a0r/w sr fig.40 read cycle ifp.
2003 nov 18 62 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H table 19 i 2 c-bus symbol description 11.2 mpi data transfer formats table 20 data transfer formats; note 1 note 1. m = msb, l = lsb and x = dont care. symbol description s start condition sr repeated start condition p stop condition r read bit (1) w write bit (0) a acknowledge from slave (SAA7724H) a acknowledge from master (microcontroller) na negative acknowledge from master to stop the data transfer device device address addrh and addrl address memory map datah, datam and datal data of xram (3 bytes) datam and datal data of yram or ifp (2 bytes) transfer from to y transfer mpi ? yram i 2 c-bus: xxxxm----------l yram: m----------l y transfer yram ? i 2 c-bus yram: m----------l i 2 c-bus: xxxxm----------l x transfer i 2 c-bus ? xram i 2 c-bus: m----------------------l xram: m----------------------l x transfer xram ? i 2 c-bus xram: m----------------------l i 2 c-bus: m----------------------l transfer i 2 c-bus ? ifp i 2 c-bus: m--------------l ifp: m--------------l transfer ifp ? i 2 c-bus ifp_data_r: m--------------l i 2 c-bus: m----------l
2003 nov 18 63 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 11.3 reset initialization with a synchronous reset the SAA7724H will turn to their idle position (state 0), the address counter is set to zero and the sda_out line remains high-impedance. for the sda line an asynchronous reset is also implemented which is connected directly to the reset pin. during the asynchronous reset period the internal sda_out line remains high which results in a high-impedance sda line. these two resets should have an overlap to have a proper initialization. it is also possible to reset the internal i 2 c-bus registers separately, and these registers will be set to their default values. 11.4 de?ned i 2 c-bus address the i 2 c-bus address is defined for location: 001110p; the least significant bit is a programmable bit with the external pin a0_pin. two possible options are available with this pin: if a0 = 0 the following addresses are available: C write: 00111000 = 38h C read: 00111001 = 39h. if a0 = 1 the following addresses are available: C write: 00111010 = 3ah C read: 00111011 = 3bh. 11.5 i 2 c-bus memory map speci?cation the i 2 c-bus memory map contains all defined i 2 c-bus bits related to rds, src and epics control and allocates epics, src and ifp ram sizes. the memory spaces belonging to the audio_epics are referred to as epics registers, and memory spaces belonging to the src/rds epics are referred to as src registers. the rds registers control the rds1 and rds2 blocks simultaneously while providing each rds1 and rds2 block with its own decoded data and status registers: the memory map is given in table 21. detailed memory map locations of the hardware registers related to the i 2 c-bus epics control are given in table 23 and the i 2 c-bus rds control are given in table 24. table 21 i 2 c-bus memory map; notes 1 and 2 block start (hex) end (hex) name number of words bit width (debug part) access - e000 ffff not used -- src b880 dfff reserved -- src b800 b87f src_yram 128 12 r/w src b000 b7ff reserved -- src afff afff iic_src_pc 1 24 r/w src affe affe iic_src_stat 1 24 r/w src a300 affd reserved -- src a000 a2ff src_xram 768 24 r/w - 9000 9fff reserved -- - 6030 8fff not used -- global 602f 602f iic_dsp_ctr 1 24 r/w - 6010 602e not used -- rds 6000 600f rds 1 and 2 registers 12 16 see table 24 epics 5fff 5fff iic_silicon_id 1 32 read epics 4000 5ffe reserved -- - 3000 3fff not used -- ifp 2c64 2fff ifp registers all 16-bit width r/w
2003 nov 18 64 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H notes 1. at all reserved spaces an acknowledge (ack) will be generated. 2. at all not used spaces a negative acknowledge (nack) will be generated. table 22 i 2 c-bus memory map src_epics hardware register overview table 23 i 2 c-bus memory map audio_epics hardware register overview - 1400 2c63 reserved -- ifp 2c00 2c63 fp_ram 100 16 r/w ifp 2700 2bff reserved -- ifp 2600 26ff vy3_ram 256 16 r/w ifp 2500 25ff vx3_ram 256 16 r/w ifp 2400 24ff vy2_ram 256 16 r/w ifp 2300 23ff vx2_ram 256 16 r/w ifp 2200 22ff vy1_ram 256 16 r/w ifp 2100 21ff vx1_ram 256 16 r/w ifp 2081 20ff reserved -- ifp 2080 2080 iic_swb_err_stat 1 16 r/w ifp 2000 207f swb_ram 128 16 r/w epics 1400 1fff reserved -- epics 1000 13ff epics_yram 1024 12 r/w epics 0fff 0fff iic_epics_pc 1 24 r/w epics 0ffe 0ffe iic_epics_stat 1 24 r/w epics 0ff0 0ffd epics registers 14 24 r/w epics 0e00 0fef reserved -- epics 0000 0dff epics_xram 3584 24 r/w location (hex) register name # used bits read/write afff iic_src_pc 24 r/w affe iic_src_stat 24 r/w location (hex) register name # used bits read/write 0fff iic_epics_pc 24 r/w 0ffe iic_epics_stat 24 r/w 0ffd iic_dspio_conf 9 r/w 0ffc iic_sel 20 r/w 0ffb iic_ifad_sel 10 r/w 0ffa iic_host 12 r/w block start (hex) end (hex) name number of words bit width (debug part) access
2003 nov 18 65 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H table 24 i 2 c-bus memory map rds hardware register overview table 25 i 2 c_epics_stat status register (0ffeh) 0ff9 iic_spdif_stat 13 read 0ff8 iic_sum 13 r/w 0ff7 iic_epics_start_addr 16 r/w location (hex) register name # used bits read/write 600f and 600e not used -- 600d iic_rds2_ctr 11 write 600c iic_rds2_set 15 write 600b iic_rds2_cnt 16 read 600a iic_rds2_pdat 16 read 6009 iic_rds2_ldat 16 read 6008 iic_rds2_stat 8 read 6007 and 6006 not used -- 6005 iic_rds1_ctr 11 write 6004 iic_rds1_set 15 write 6003 iic_rds1_cnt 16 read 6002 iic_rds1_pdat 16 read 6001 iic_rds1_ldat 16 read 6000 iic_rds1_stat 8 read bit symbol default description 23 to 13 - 0h internal ?ags 12 and 11 f12 and f11 - not used 10 f10 0 spdif2 lock status 0: not locked 1: locked 9 f9 0 spdif1 lock status 0: not locked 1: locked 8 f8 0 dspio8 status 0: input 1: output 7 f7 0 dspio7 status 0: input 1: output 6 f6 0 dspio6 status 0: input 1: output location (hex) register name # used bits read/write
2003 nov 18 66 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H table 26 iic_dspio_conf con?guration register (0ffdh) 5 f5 0 dspio5 status 0: input 1: output 4 f4 0 dspio4 status 0: input 1: output 3 f3 0 dspio3 status 0: input 1: output 2 f2 0 dspio2 status 0: input 1: output 1 f1 0 dspio1 status 0: input 1: output 0 f0 0 dspio0 status 0: input 1: output bit symbol default description 23 to 9 -- not used 8 con?g_dspio8 0 port con?guration for dspio8 0: input 1: output 7 con?g_dspio7 0 port con?guration for dspio7 0: input 1: output 6 con?g_dspio6 0 port con?guration for dspio6 0: input 1: output 5 con?g_dspio5 0 port con?guration for dspio5 0: input 1: output 4 con?g_dspio4 0 port con?guration for dspio4 0: input 1: output 3 con?g_dspio3 0 port con?guration for dspio3 0: input 1: output bit symbol default description
2003 nov 18 67 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H table 27 iic_sel selection register (0ffch) 2 con?g_dspio2 0 port con?guration for dspio2 0: input 1: output 1 con?g_dspio1 0 port con?guration for dspio1 0: input 1: output 0 con?g_dspio0 0 port con?guration for dspio0 0: input 1: output bit symbol default description 23 to 20 -- not used 19 ch2_dc_offset 1 dc offset ?lter for audio channel 2 0: disable 1: enable 18 ch1_dc_offset 1 dc offset ?lter for audio channel 1 0: disable 1: enable 17 aux2_sel_lev_ voice 0 select behavioural of the compensation ?lter for aux channel 2 0: level inputs 1: voice inputs 16 aux1_sel_lev_ voice 0 select behavioural of the compensation ?lter for aux channel 1 0: level inputs 1: voice inputs 15 ch2_wide_narrow 0 select bandwidth for audio channel 2 0: audio + rds information 1: only audio data 14 ch1_wide_narrow 0 select bandwidth for audio channel 1 0: audio + rds information 1: only audio data 13 sel_spdif2_iis2 0 select input for src2 0: spdif 2 1: ext_iis2 12 sel_spdif1_iis1 0 select input for src1 0: spdif 1 1: ext_iis1 11 and 10 aic3[1:0] 11 analog input control 3; see table 6 9 s2 1 ad normal/differential selection 2; see table 4 8 intref2 0 ad internal reference 2; see table 4 7 and 6 aic2[1:0] 01 analog input control 2; see table 5 bit symbol default description
2003 nov 18 68 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H table 28 iic_ifad_sel selection register (0ffbh) table 29 iic_host register (0ffah) 5 refc2 1 ad reference control 2; see table 4 4 s1 0 ad normal/differential selection 1; see table 4 3 intref1 0 ad internal reference 1; see table 4 2 and 1 aic1[1:0] 00 analog input control 1; see table 5 0 refc1 0 ad reference control 1; see table 4 bit symbol default description 23 to 10 -- not used 9 ifad2_power 1 controls activity of ifad2 0: power low 1: power on 8 ifad1_power 1 controls activity of ifad1 0: power low 1: power on 7 to 4 dith_gain_2[3:0] 0000 control gain of if-ad dither source 2 3 to 0 dith_gain_1[3:0] 0000 control gain of if-ad dither source 1 bit symbol default description 23 to 20 -- not used 19 src2_ext_sel_out 0 selects the external output port for src2 0: ext_iis1 1: ext_iis2 18 src1_ext_sel_out 1 selects the external output port for src1 0: ext_iis1 1: ext_iis2 17 src2_int_ext_out 0 selects the output destination for src2 0: internal (audio epics) 1: external (ext_iis) 16 src1_int_ext_out 0 selects the output destination for src1 0: internal (audio epics) 1: external (ext_iis) 15 src2_int_ext_in 1 selects the input source for src2 0: internal (audio epics) 1: external (ext_iis/spdif) 14 src1_int_ext_in 1 selects the input source for src1 0: internal (audio epics) 1: external (ext_iis/spdif) bit symbol default description
2003 nov 18 69 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H table 30 iic_spdif_stat status register (0ff9h) 13 en_ifp_iis_bck 0 enable ifp_iis_bck 0: disable 1: enable 12 iboc_mode 0 selects outputs of if decimation paths to come out at ifp_iis ports 0: disable 1: enable 11 to 9 ext_host_io_ format2[2:0] 000 input data format for ext_iis2 port; see table 10 8 to 6 ext_host_io_ format1[2:0] 000 input data format for ext_iis1 port; see table 10 5 en_host_io 0 port output enable for iis_out port 0: disable. iis_out1, iis_out2 and iis_out3 set to zero; iis_ws and iis_bck 3-stated 1: all pins enabled 4 to 2 host_io_format[2:0] 000 host input/output data format for i 2 s-bus port; see table 12 1 -- not used 0 en_256fs 0 256 f s clock output 0: disable 1: enable bit symbol default description 23 to 17 -- not used 16 ifp_status - ifp_status 0: disabled 1: enabled 15 and 14 -- not used 13 and 12 spdif2_ accuracy[1:0] - accuracy of sampling frequency of spdif2 channel 00: level ii 10: level iii 01: level i 11: reserved 11 and 10 spdif2_fs[1:0] - audio sampling frequency of spdif2 channel 00: 44.1 khz 10: 48 khz 01: reserved 11: 32 khz 9 spdif2_emphasis - equalization of spdif2 channel 0: no pre-emphasis present 1: 50/15 m s pre-emphasis present bit symbol default description
2003 nov 18 70 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H table 31 iic_sum summer register (0ff8h) 8 spdif2_content - contents of spdif2 channel 0: normal audio mode 1: data mode 7 and 6 -- not used 5 and 4 spdif1_ accuracy[1:0] - accuracy of sampling frequency of spdif1 channel 00: level ii 10: level iii 01: level i 11: reserved 3 and 2 spdif1_fs[1:0] - audio sampling frequency of spdif1 channel 00: 44.1 khz 10: 48 khz 01: reserved 11: 32 khz 1 spdif1_emphasis - equalization of spdif1 channel 0: no pre-emphasis present 1: 50/15 m s pre-emphasis present 0 spdif1_content - contents of spdif1 channel 0: normal audio mode 1: data mode bit symbol default description 23 to 13 -- not used 12 rrm 0 dac summer rr enable; see table 9 11 rlm 0 dac summer rl enable; see table 9 10 frm 0 dac summer fr enable; see table 9 9 ?m 0 dac summer fl enable; see table 9 8 mixc 0 dac summer input selection 0: mono1 1: mono2 7 i?n2_inpsel 0 select ifad for ifin2 input from ifp 0: for if_ad2 1: for if_ad1 6 i?n1_inpsel 0 select ifad for ifin1 input from ifp 0: for if_ad1 1: for if_ad2 5 to 0 volmix[5:0] 000000 dac summer volume setting; see table 8 bit symbol default description
2003 nov 18 71 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H table 32 iic_epics_start_addr address register (0ff7h) table 33 iic_dsp_ctr control register (602fh) table 34 iic_silicon_id register (5fffh); bit symbol default description 23 to 16 -- not used 15 to 0 start_addr[15:0] 0000h start address for the audio_epics; can be programmed before releasing epics_pc_reset bit; see table 33 bit symbol default description 23 to 19 -- not used 18 and 17 pll2_clksel[1:0] 01 choose pll2 clock selection switch 00: low range 01: mid range 16 and 15 pll1_clksel[1:0] 00 choose pll1 clock selection switch 00: low range 01: mid range 14 to 10 pll2_div[4:0] 01101 choose pll2 division factor 9 to 5 pll1_div[4:0] 10000 choose pll1 division factor 4 pll2_bypass 0 bypass option for src_epics; this is an evaluation mode only 0: pll2 1: oscin_clk 3 pll1_bypass 0 bypass option for audio_epics clock; warning: the oscin_clk is only used for evaluation; it is functionally not a valid setting 0: pll2 1: oscin_clk 2 -- not used 1 src_pc_reset 1 program counter for src_epics reset 0: no reset 1: reset; program counter will always be set to 0000h 0 epics_pc_reset 1 program counter for audio_epics reset 0: no reset 1: reset; program counter will be set to the start_addr value; see table 32 bit symbol default description 31 to 16 dev_number[15:0] - development number; decimal number 15 to 12 dev_version[3:0] - development version number; binary code 11 to 7 mask_version[4:0] - mask version number; binary code 6 to 0 romcode_ version[6:0] - rom code version number; binary code
2003 nov 18 72 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H table 35 iic_rds2_ctr control register (600dh) table 36 description of bits rds2_clkout and rds2_clkin table 37 description of bits rds2_dac1 and rds0_dac0 table 38 iic_rds2_set settings register (600ch) bit symbol default description 15 to 11 -- not used 10 sel_davn2_rds_ flag 0 select davn2 control indicator 0: use rds2 block 1: use flag from ifp 9 rds2_clkout 0 see table 36 8 rds2_clkin 1 7 and 6 rds2_dac[1:0] 00 see table 37 5 rds2_nwsy 0 start new synchronization 0: no start 1: start 4 to 0 rds2_mbbg[4:0] 00000 maximum bad blocks gain rds2_clkout rds2_clkin description 0 0 rds decoder 0 1 burst mode with external clock as input 1 0 rds demodulator 1 1 not allowed rds2_dac1 rds2_dac0 description 0 0 standard mode 0 1 fast pi search mode 1 0 reduced data request 1 1 decoder bypass bit symbol default description 15 -- not used 14 and 13 rds2_sym[1:0] 00 see table 39 12 to 7 rds2_mgbl[5:0] 100000 maximum good blocks lose 6 rds2_rbds 0 allow rbds e blocks 0: not allow 1: allow 5 to 0 rds2_mbbl[5:0] 100000 maximum bad blocks lose
2003 nov 18 73 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H table 39 description of bits rds2_sym1 and rds2_sym0 table 40 iic_rds2_cnt counter register (600bh) table 41 description of bits rds2_epb1 and rds2_epb0 table 42 iic_rds2_pdat register (600ah) table 43 iic_rds2_ldat register (6009h) table 44 iic_rds2_stat status register (6008h) rds2_sym1 rds2_symo description 0 0 no error correction 0 1 maximum 2 bits burst error 1 0 maximum 5 bits burst error 1 1 no error correction bit symbol default description 15 to 10 rds2_bbc[5:0] 000000 bad blocks counter 9 to 5 rds2_gbc[4:0] 00000 good blocks counter (only 5 msbs are available) 4 to 2 rds2_pbin[2:0] 111 previous block identi?er 1 and 0 rds2_epb[1:0] 00 error status previously received block; see table 41 rds2_epb1 rds2_epb0 description 0 0 no errors detected 0 1 maximum 2 bits 1 0 maximum 5 bits 1 1 uncorrectable bit symbol default description 15 to 0 rds2_pdat[15:0] 0000h previously processed block data bit symbol default description 15 to 0 rds2_ldat[15:0] 0000h last processed block data bit symbol default description 15 to 8 -- not used 7 rds2_sync 0 synchronization found 0: no synchronization 1: synchronization 6 rds2_dofl 0 data over?ow ?ag 0: no overflow 1: overflow
2003 nov 18 74 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H table 45 description of bits rds2_elb1 and rds2_elb0 table 46 iic_rds1_ctr control register (6005h) table 47 description of bits rds1_clkout and rds1_clkin 5 rds2_rstd 0 reset detected 0: no reset 1: reset 4 to 2 rds2_lbin[2:0] 111 last block identi?cation 1 and 0 rds2_elb[1:0] 00 error status last block; see table 45 rds2_elb1 rds2_elb0 description 0 0 no errors detected 0 1 maximum 2 bits 1 0 maximum 5 bits 1 1 uncorrectable bit symbol default description 15 to 11 -- not used 10 sel_rds_clk1_ davn2 0 select usage for pin rds_clk1_davn2; pin is used for davn2 and ifp ?ag usage (depending on state of sel_davn2_rds_flag); otherwise pin is used as rds_clk1 for rds1 block 1: davn2 and ifp flag usage 0: rds_clk1 9 rds1_clkout 0 see table 47 8 rds1_clkin 1 7 and 6 rds1_dac[1:0] 00 see table 48 5 rds1_nwsy 0 start new synchronization 0: no start 1: start 4 to 0 rds1_mbbg[4:0] 00000 max bad blocks gain rds1_clkout rds1_clkin description 0 0 decoder 0 1 burst mode with external clock as input 1 0 demodulator 1 1 not allowed bit symbol default description
2003 nov 18 75 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H table 48 description of bits rds1_dac1 and rds1_dac0 table 49 iic_rds1_set settings register (6004h) table 50 description of bits rds1_sym1 and rds1_sym0 table 51 iic_rds1_cnt counter register (6003h) table 52 description of bits rds1_epb1 and rds1_epb0 rds1_dac1 rds1_dac0 description 0 0 standard mode 0 1 fast pi search mode 1 0 reduced data request 1 1 decoder bypass bit symbol default description 15 -- not used 14 and 13 rds1_sym[1:0] 00 see table 50 12 to 7 rds1_mgbl[5:0] 100000 maximum good blocks lose 6 rds1_rbds 0 allow rbds e blocks 0: not allowed 1: allowed 5 to 0 rds1_mbbl[5:0] 100000 maximum bad blocks lose rds1_sym1 rds1_sym0 description 0 0 no error correction 0 1 maximum 2 bits burst error 1 0 maximum 5 bits burst error 1 1 no error correction bit symbol default description 15 to 10 rds1_bbc[5:0] 000000 bad blocks counter 9 to 5 rds1_gbc[4:0] 00000 good blocks counter (only 5 msbs are available) 4 to 2 rds1_pbin[2:0] 111 previous block identi?er 1 and 0 rds1_epb[1:0] 00 error status previously received block; see table 52 rds1_epb1 rds1_epb0 description 0 0 no errors detected 0 1 maximum 2 bits 1 0 maximum 5 bits 1 1 uncorrectable
2003 nov 18 76 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H table 53 iic_rds1_pdat register (6002h) table 54 iic_rds1_ldat register (6001h) table 55 iic_rds1_stat status register (6000h) table 56 description of bits rds1_elb1 and rds1_elb0 bit symbol default description 15 to 0 rds1_pdat[15:0] 0000h previously processed block data bit symbol default description 15 to 0 rds1_ldat[15:0] 0000h last processed block data bit symbol default description 15 to 8 - - not used 7 rds1_sync 0 synchronization found 0: no synchronization 1: synchronization 6 rds1_dofl 0 data over?ow ?ag 0: no overflow 1: overflow 5 rds1_rstd 0 reset detected 0: no reset 1: reset 4 to 2 rds1_lbin[2:0] 111 last block identi?cation 1 and 0 rds1_elb[1:0] 00 error status last block; see table 56 rds1_elb1 rds1_elb0 description 0 0 no errors detected 0 1 maximum 2 bits 1 0 maximum 5 bits 1 1 uncorrectable
2003 nov 18 77 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 12 i 2 s-bus control 12.1 basic system requirements the inter-ic sound (i 2 s-bus) was developed by philips to facilitate communications between the ever increasing number of digital audio processing ics in a typical audio system. the bus only has to handle audio data, while the other signals such as sub-coding and control are transferred separately. to minimize the number of pins required and to keep wiring simple, a 3-line serial bus is used consisting of a line for two time-multiplexed data channels, a word select line and a clock line. since the transmitter and receiver have the same clock signal for data transmission, the transmitter as the master, has to generate the bit clock, word select signal and data. in complex systems however, there may be several transmitters and receivers which makes it difficult to define the master. in such systems there is usually a system master controlling digital audio data-flow between the various ics. transmitters then have to generate data under the control of an external clock, and so act as a slave. figure 41 illustrates some simple system configurations and the basic interface timing. note that the system master can be combined with a transmitter or receiver, and it may be enabled or disabled under software control or by pin programming. as shown in fig.41, the bus has three lines: continuous serial clock (sck) word select (ws) serial data (sd). the device generating sck and ws is the master. handbook, full pagewidth mgw230 ws receiver receiver = master transmitter sck sd word select ws receiver transmitter = master transmitter clock sck data sd ws receiver msb sck ws sd word n left channel word n + 1 right channel word n - 1 right channel lsb msb controller = master transmitter controller sck sd fig.41 simple system configurations and basic interface timing.
2003 nov 18 78 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 12.2 serial data serial data is transmitted in twos complement with the msb first. the msb is transmitted first because the transmitter and receiver may have different word lengths. it is not necessary for the transmitter to know how many bits the receiver can handle, nor does the receiver need to know how many bits are being transmitted. when the system word length is greater than the transmitter word length, the word is truncated (least significant bits are set to 0) for data transmission. if the receiver is sent more bits than its word length, the bits after the lsb are ignored. however, if the receiver is sent fewer bits than its word length the missing bits are set to zero internally. therefore, the msb has a fixed position whereas the position of the lsb depends on the word length. the transmitter always sends the msb of the next word one clock period after the ws changes. serial data sent by the transmitter may be synchronized with either the trailing (high-to-low) or the leading (low-to-high) edge of the clock signal. however, the serial data must be latched into the receiver on the leading edge of the serial clock signal so there are some restrictions when transmitting data that is synchronized with the leading edge. 12.3 word select the word select line indicates the channel being transmitted: ws = 0: channel 1 (left) ws = 1: channel 2 (right). ws may change either on a trailing or leading edge of the serial clock, but it doesnt need to be symmetrical. in the slave, this signal is latched on the leading edge of the clock signal. the ws line changes one clock period before the msb is transmitted. this allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission. furthermore, it enables the receiver to store the previous word and clear the input for the next word (see fig.41).
2003 nov 18 79 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 13 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 0.45 0.25 2.90 2.65 0.25 0.40 0.25 0.25 0.14 14.1 13.9 0.65 18.2 17.6 1.0 0.6 7 0 o o 0.15 0.1 0.2 1.95 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.73 sot317-3 mo-112 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 0.8 0.4 d e q e a 1 a l p detail x l (a ) 3 b 30 c b p e h a 2 d z d a z e e v m a 1 100 81 80 51 50 31 pin 1 index x y b p d h v m b w m w m 0 5 10 mm scale qfp100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot317-3 a max. 3.4 99-12-15 03-02-25
2003 nov 18 80 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 14 soldering 14.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 14.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson-t and ssop-t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2003 nov 18 81 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 14.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the reflow oven. the package body peak temperature must be kept as low as possible. 4. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 6. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on flex foil. however, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. the appropriate soldering profile can be provided on request. 9. hot bar or manual soldering is suitable for pmfp packages. package (1) soldering method wave reflow (2) bga, htsson..t (3) , lbga, lfbga, sqfp, ssop..t (3) , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable (4) suitable plcc (5) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (5)(6) suitable ssop, tssop, vso, vssop not recommended (7) suitable cwqccn..l (8) , pmfp (9) , wqccn..l (8) not suitable not suitable
2003 nov 18 82 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 15 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 16 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 17 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 nov 18 83 philips semiconductors preliminary speci?cation car radio digital signal processor SAA7724H 18 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 753503/02/pp 84 date of release: 2003 nov 18 document order number: 9397 750 11426

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